drm/amdgpu: add structures for rlcg indirect reg access
Add structures that are used to cache registers offsets for rlcg indirect reg access ctrl and flag availability of such interface Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Zhou, Peng Ju <PengJu.Zhou@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -132,6 +132,16 @@ struct amdgpu_rlc_funcs {
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bool (*is_rlcg_access_range)(struct amdgpu_device *adev, uint32_t reg);
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};
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struct amdgpu_rlcg_reg_access_ctrl {
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uint32_t scratch_reg0;
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uint32_t scratch_reg1;
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uint32_t scratch_reg2;
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uint32_t scratch_reg3;
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uint32_t grbm_cntl;
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uint32_t grbm_idx;
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uint32_t spare_int;
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};
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struct amdgpu_rlc {
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/* for power gating */
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struct amdgpu_bo *save_restore_obj;
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@ -191,6 +201,10 @@ struct amdgpu_rlc {
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struct amdgpu_bo *rlc_toc_bo;
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uint64_t rlc_toc_gpu_addr;
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void *rlc_toc_buf;
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bool rlcg_reg_access_supported;
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/* registers for rlcg indirect reg access */
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struct amdgpu_rlcg_reg_access_ctrl reg_access_ctrl;
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};
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void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev);
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