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drm/msm/adreno: Expose speedbin to userspace

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Expose speedbin through MSM_PARAM_CHIP_ID parameter to help userspace
identify the sku.

Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
Link: https://lore.kernel.org/r/20220226005021.v2.4.I86c32730e08cba9e5c83f02ec17885124d45fa56@changeid
Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Akhil P Oommen 2022-02-26 00:51:31 +05:30 committed by Rob Clark
parent c43de1aa6a
commit afab9d91d8
3 changed files with 21 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
View File

@ -10,7 +10,6 @@
#include <linux/bitfield.h>
#include <linux/devfreq.h>
#include <linux/nvmem-consumer.h>
#include <linux/soc/qcom/llcc-qcom.h>
#define GPU_PAS_ID 13
@ -1774,7 +1773,7 @@ static int a6xx_set_supported_hw(struct device *dev, struct adreno_rev rev)
u32 speedbin;
int ret;
ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin", &speedbin);
ret = adreno_read_speedbin(dev, &speedbin);
/*
* -ENOENT means that the platform doesn't support speedbin which is
* fine

21
drivers/gpu/drm/msm/adreno/adreno_gpu.c
View File

@ -14,6 +14,7 @@
#include <linux/pm_opp.h>
#include <linux/slab.h>
#include <linux/soc/qcom/mdt_loader.h>
#include <linux/nvmem-consumer.h>
#include <soc/qcom/ocmem.h>
#include "adreno_gpu.h"
#include "a6xx_gpu.h"
@ -243,10 +244,12 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
*value = !adreno_is_a650_family(adreno_gpu) ? 0x100000 : 0;
return 0;
case MSM_PARAM_CHIP_ID:
*value = adreno_gpu->rev.patchid |
(adreno_gpu->rev.minor << 8) |
(adreno_gpu->rev.major << 16) |
(adreno_gpu->rev.core << 24);
*value = (uint64_t) adreno_gpu->rev.patchid |
(uint64_t) (adreno_gpu->rev.minor << 8) |
(uint64_t) (adreno_gpu->rev.major << 16) |
(uint64_t) (adreno_gpu->rev.core << 24);
if (!adreno_gpu->info->revn)
*value |= ((uint64_t) adreno_gpu->speedbin) << 32;
return 0;
case MSM_PARAM_MAX_FREQ:
*value = adreno_gpu->base.fast_rate;
@ -922,6 +925,11 @@ void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem)
adreno_ocmem->hdl);
}
int adreno_read_speedbin(struct device *dev, u32 *speedbin)
{
return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin);
}
int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
struct adreno_gpu *adreno_gpu,
const struct adreno_gpu_funcs *funcs, int nr_rings)
@ -932,6 +940,7 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
struct msm_gpu *gpu = &adreno_gpu->base;
struct adreno_rev *rev = &config->rev;
const char *gpu_name;
u32 speedbin;
adreno_gpu->funcs = funcs;
adreno_gpu->info = adreno_info(config->rev);
@ -939,6 +948,10 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
adreno_gpu->revn = adreno_gpu->info->revn;
adreno_gpu->rev = *rev;
if (adreno_read_speedbin(dev, &speedbin) || !speedbin)
speedbin = 0xffff;
adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
gpu_name = adreno_gpu->info->name;
if (!gpu_name) {
gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%d.%d.%d.%d",

3
drivers/gpu/drm/msm/adreno/adreno_gpu.h
View File

@ -80,6 +80,7 @@ struct adreno_gpu {
const struct adreno_info *info;
uint32_t gmem; /* actual gmem size */
uint32_t revn; /* numeric revision name */
uint16_t speedbin;
const struct adreno_gpu_funcs *funcs;
/* interesting register offsets to dump: */
@ -325,6 +326,8 @@ adreno_iommu_create_address_space(struct msm_gpu *gpu,
void adreno_set_llc_attributes(struct iommu_domain *iommu);
int adreno_read_speedbin(struct device *dev, u32 *speedbin);
/*
* For a5xx and a6xx targets load the zap shader that is used to pull the GPU
* out of secure mode