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drm/msm/a6xx: Add support for 7c3 SKUs

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Add support for 7c3 SKU detection using speedbin fuse.

Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
Link: https://lore.kernel.org/r/20220226005021.v2.3.I6e89c014eb17f090f716fba662bdd33073920804@changeid
Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Akhil P Oommen 2022-02-26 00:51:30 +05:30 committed by Rob Clark
parent e2f7619395
commit c43de1aa6a
1 changed files with 15 additions and 0 deletions
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15
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
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@ -1736,6 +1736,18 @@ static u32 a618_get_speed_bin(u32 fuse)
return UINT_MAX;
}
static u32 adreno_7c3_get_speed_bin(u32 fuse)
{
if (fuse == 0)
return 0;
else if (fuse == 117)
return 0;
else if (fuse == 190)
return 1;
return UINT_MAX;
}
static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse)
{
u32 val = UINT_MAX;
@ -1743,6 +1755,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse)
if (adreno_cmp_rev(ADRENO_REV(6, 1, 8, ANY_ID), rev))
val = a618_get_speed_bin(fuse);
if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev))
val = adreno_7c3_get_speed_bin(fuse);
if (val == UINT_MAX) {
DRM_DEV_ERROR(dev,
"missing support for speed-bin: %u. Some OPPs may not be supported by hardware",