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clk: pwm: Use 64-bit division function

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Since the PWM framework is switching struct pwm_args.period's datatype
to u64, prepare for this transition by using div64_u64() to handle a
64-bit divisor.

Also ensure that divide-by-zero (with fixed_rate as denominator) does
not happen with an explicit check with probe failure as a consequence.

Signed-off-by: Guru Das Srinagesh <gurus@codeaurora.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
This commit is contained in:
Guru Das Srinagesh 2020-06-02 15:31:15 -07:00 committed by Thierry Reding
parent 134ada17db
commit a6733474ba
1 changed files with 6 additions and 1 deletions
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7
drivers/clk/clk-pwm.c
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@ -89,7 +89,12 @@ static int clk_pwm_probe(struct platform_device *pdev)
}
if (of_property_read_u32(node, "clock-frequency", &clk_pwm->fixed_rate))
clk_pwm->fixed_rate = NSEC_PER_SEC / pargs.period;
clk_pwm->fixed_rate = div64_u64(NSEC_PER_SEC, pargs.period);
if (!clk_pwm->fixed_rate) {
dev_err(&pdev->dev, "fixed_rate cannot be zero\n");
return -EINVAL;
}
if (pargs.period != NSEC_PER_SEC / clk_pwm->fixed_rate &&
pargs.period != DIV_ROUND_UP(NSEC_PER_SEC, clk_pwm->fixed_rate)) {