arm64: dts: hi3660: add resources for clock and reset
Add some resource nodes for clock and reset Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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@ -5,6 +5,7 @@
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/hi3660-clock.h>
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/ {
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compatible = "hisilicon,hi3660";
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@ -141,18 +142,56 @@
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#size-cells = <2>;
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ranges;
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fixed_uart5: fixed_19_2M {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <19200000>;
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clock-output-names = "fixed:uart5";
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crg_ctrl: crg_ctrl@fff35000 {
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compatible = "hisilicon,hi3660-crgctrl", "syscon";
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reg = <0x0 0xfff35000 0x0 0x1000>;
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#clock-cells = <1>;
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};
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uart5: uart@fdf05000 {
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crg_rst: crg_rst_controller {
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compatible = "hisilicon,hi3660-reset";
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#reset-cells = <2>;
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hisi,rst-syscon = <&crg_ctrl>;
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};
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pctrl: pctrl@e8a09000 {
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compatible = "hisilicon,hi3660-pctrl", "syscon";
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reg = <0x0 0xe8a09000 0x0 0x2000>;
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#clock-cells = <1>;
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};
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pmuctrl: crg_ctrl@fff34000 {
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compatible = "hisilicon,hi3660-pmuctrl", "syscon";
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reg = <0x0 0xfff34000 0x0 0x1000>;
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#clock-cells = <1>;
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};
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sctrl: sctrl@fff0a000 {
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compatible = "hisilicon,hi3660-sctrl", "syscon";
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reg = <0x0 0xfff0a000 0x0 0x1000>;
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#clock-cells = <1>;
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};
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iomcu: iomcu@ffd7e000 {
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compatible = "hisilicon,hi3660-iomcu", "syscon";
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reg = <0x0 0xffd7e000 0x0 0x1000>;
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#clock-cells = <1>;
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};
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iomcu_rst: reset {
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compatible = "hisilicon,hi3660-reset";
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hisi,rst-syscon = <&iomcu>;
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#reset-cells = <2>;
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};
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uart5: serial@fdf05000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0xfdf05000 0x0 0x1000>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&fixed_uart5 &fixed_uart5>;
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clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>,
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<&crg_ctrl HI3660_CLK_GATE_UART5>;
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clock-names = "uartclk", "apb_pclk";
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status = "disabled";
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};
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