forked from Minki/linux
pinctrl/rockchip: drop the gpio related codes
With the patch to separate the gpio driver from the pinctrl driver, now the pinctrl-rockchip can drop the gpio related codes now. Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Link: https://lore.kernel.org/r/20210816012146.1119289-1-jay.xu@rock-chips.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Jianqun Xu
Linus Walleij
parent
93103f6eb0
commit
9ce9a02039
@ -21,8 +21,8 @@
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#include <linux/io.h>
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#include <linux/bitops.h>
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#include <linux/gpio/driver.h>
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#include <linux/of_device.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/pinctrl/machine.h>
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#include <linux/pinctrl/pinconf.h>
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@ -39,20 +39,6 @@
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#include "pinconf.h"
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#include "pinctrl-rockchip.h"
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/* GPIO control registers */
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#define GPIO_SWPORT_DR 0x00
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#define GPIO_SWPORT_DDR 0x04
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#define GPIO_INTEN 0x30
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#define GPIO_INTMASK 0x34
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#define GPIO_INTTYPE_LEVEL 0x38
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#define GPIO_INT_POLARITY 0x3c
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#define GPIO_INT_STATUS 0x40
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#define GPIO_INT_RAWSTATUS 0x44
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#define GPIO_DEBOUNCE 0x48
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#define GPIO_PORTS_EOI 0x4c
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#define GPIO_EXT_PORT 0x50
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#define GPIO_LS_SYNC 0x60
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/**
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* Generate a bitmask for setting a value (v) with a write mask bit in hiword
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* register 31:16 area.
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@ -2071,75 +2057,11 @@ static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
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return 0;
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}
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static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
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{
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struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
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u32 data;
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data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
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if (data & BIT(offset))
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return GPIO_LINE_DIRECTION_OUT;
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return GPIO_LINE_DIRECTION_IN;
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}
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/*
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* The calls to gpio_direction_output() and gpio_direction_input()
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* leads to this function call (via the pinctrl_gpio_direction_{input|output}()
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* function called from the gpiolib interface).
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*/
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static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
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int pin, bool input)
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{
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struct rockchip_pin_bank *bank;
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int ret;
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unsigned long flags;
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u32 data;
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bank = gpiochip_get_data(chip);
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ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
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if (ret < 0)
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return ret;
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raw_spin_lock_irqsave(&bank->slock, flags);
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data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
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/* set bit to 1 for output, 0 for input */
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if (!input)
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data |= BIT(pin);
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else
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data &= ~BIT(pin);
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writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
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raw_spin_unlock_irqrestore(&bank->slock, flags);
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return 0;
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}
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static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned offset, bool input)
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{
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struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
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struct gpio_chip *chip;
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int pin;
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chip = range->gc;
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pin = offset - chip->base;
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dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
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offset, range->name, pin, input ? "input" : "output");
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return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
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input);
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}
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static const struct pinmux_ops rockchip_pmx_ops = {
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.get_functions_count = rockchip_pmx_get_funcs_count,
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.get_function_name = rockchip_pmx_get_func_name,
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.get_function_groups = rockchip_pmx_get_groups,
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.set_mux = rockchip_pmx_set,
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.gpio_set_direction = rockchip_pmx_gpio_set_direction,
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};
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/*
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@ -2170,15 +2092,13 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
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return false;
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}
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static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
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static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
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/* set the pin config settings for a specified pin */
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static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
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unsigned long *configs, unsigned num_configs)
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{
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struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
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struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
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struct gpio_chip *gpio = &bank->gpio_chip;
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enum pin_config_param param;
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u32 arg;
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int i;
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@ -2211,10 +2131,13 @@ static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
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return rc;
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break;
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case PIN_CONFIG_OUTPUT:
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rockchip_gpio_set(&bank->gpio_chip,
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pin - bank->pin_base, arg);
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rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
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pin - bank->pin_base, false);
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rc = rockchip_set_mux(bank, pin - bank->pin_base,
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RK_FUNC_GPIO);
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if (rc != RK_FUNC_GPIO)
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return -EINVAL;
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rc = gpio->direction_output(gpio, pin - bank->pin_base,
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arg);
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if (rc)
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return rc;
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break;
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@ -2252,6 +2175,7 @@ static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
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{
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struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
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struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
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struct gpio_chip *gpio = &bank->gpio_chip;
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enum pin_config_param param = pinconf_to_config_param(*config);
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u16 arg;
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int rc;
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@ -2280,7 +2204,7 @@ static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
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if (rc != RK_FUNC_GPIO)
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return -EINVAL;
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rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
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rc = gpio->get(gpio, pin - bank->pin_base);
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if (rc < 0)
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return rc;
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@ -2518,7 +2442,7 @@ static int rockchip_pinctrl_register(struct platform_device *pdev,
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ctrldesc->npins = info->ctrl->nr_pins;
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pdesc = pindesc;
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for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
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for (bank = 0, k = 0; bank < info->ctrl->nr_banks; bank++) {
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pin_bank = &info->ctrl->pin_banks[bank];
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for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
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pdesc->number = k;
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@ -2538,526 +2462,9 @@ static int rockchip_pinctrl_register(struct platform_device *pdev,
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return PTR_ERR(info->pctl_dev);
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}
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for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
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pin_bank = &info->ctrl->pin_banks[bank];
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pin_bank->grange.name = pin_bank->name;
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pin_bank->grange.id = bank;
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pin_bank->grange.pin_base = pin_bank->pin_base;
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pin_bank->grange.base = pin_bank->gpio_chip.base;
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pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
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pin_bank->grange.gc = &pin_bank->gpio_chip;
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pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
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}
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return 0;
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}
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/*
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* GPIO handling
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*/
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static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
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{
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struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
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void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
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unsigned long flags;
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u32 data;
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raw_spin_lock_irqsave(&bank->slock, flags);
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data = readl(reg);
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data &= ~BIT(offset);
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if (value)
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data |= BIT(offset);
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writel(data, reg);
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raw_spin_unlock_irqrestore(&bank->slock, flags);
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}
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/*
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* Returns the level of the pin for input direction and setting of the DR
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* register for output gpios.
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*/
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static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
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{
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struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
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u32 data;
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data = readl(bank->reg_base + GPIO_EXT_PORT);
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data >>= offset;
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data &= 1;
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return data;
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}
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/*
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* gpiolib gpio_direction_input callback function. The setting of the pin
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* mux function as 'gpio input' will be handled by the pinctrl subsystem
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* interface.
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*/
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static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
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{
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return pinctrl_gpio_direction_input(gc->base + offset);
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}
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/*
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* gpiolib gpio_direction_output callback function. The setting of the pin
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* mux function as 'gpio output' will be handled by the pinctrl subsystem
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* interface.
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*/
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static int rockchip_gpio_direction_output(struct gpio_chip *gc,
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unsigned offset, int value)
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{
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rockchip_gpio_set(gc, offset, value);
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return pinctrl_gpio_direction_output(gc->base + offset);
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}
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static void rockchip_gpio_set_debounce(struct gpio_chip *gc,
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unsigned int offset, bool enable)
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{
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struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
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void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE;
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unsigned long flags;
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u32 data;
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raw_spin_lock_irqsave(&bank->slock, flags);
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data = readl(reg);
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if (enable)
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data |= BIT(offset);
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else
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data &= ~BIT(offset);
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writel(data, reg);
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raw_spin_unlock_irqrestore(&bank->slock, flags);
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}
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/*
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* gpiolib set_config callback function. The setting of the pin
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* mux function as 'gpio output' will be handled by the pinctrl subsystem
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* interface.
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*/
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static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
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unsigned long config)
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{
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enum pin_config_param param = pinconf_to_config_param(config);
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switch (param) {
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case PIN_CONFIG_INPUT_DEBOUNCE:
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rockchip_gpio_set_debounce(gc, offset, true);
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/*
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* Rockchip's gpio could only support up to one period
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* of the debounce clock(pclk), which is far away from
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* satisftying the requirement, as pclk is usually near
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* 100MHz shared by all peripherals. So the fact is it
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* has crippled debounce capability could only be useful
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* to prevent any spurious glitches from waking up the system
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* if the gpio is conguired as wakeup interrupt source. Let's
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* still return -ENOTSUPP as before, to make sure the caller
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* of gpiod_set_debounce won't change its behaviour.
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*/
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return -ENOTSUPP;
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default:
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return -ENOTSUPP;
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}
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}
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/*
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* gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
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* and a virtual IRQ, if not already present.
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*/
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static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
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{
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struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
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unsigned int virq;
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if (!bank->domain)
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return -ENXIO;
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virq = irq_create_mapping(bank->domain, offset);
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return (virq) ? : -ENXIO;
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}
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static const struct gpio_chip rockchip_gpiolib_chip = {
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.request = gpiochip_generic_request,
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.free = gpiochip_generic_free,
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.set = rockchip_gpio_set,
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.get = rockchip_gpio_get,
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.get_direction = rockchip_gpio_get_direction,
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.direction_input = rockchip_gpio_direction_input,
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.direction_output = rockchip_gpio_direction_output,
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.set_config = rockchip_gpio_set_config,
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.to_irq = rockchip_gpio_to_irq,
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.owner = THIS_MODULE,
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};
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/*
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* Interrupt handling
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*/
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static void rockchip_irq_demux(struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
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u32 pend;
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dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
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chained_irq_enter(chip, desc);
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pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
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while (pend) {
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unsigned int irq, virq;
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irq = __ffs(pend);
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pend &= ~BIT(irq);
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virq = irq_find_mapping(bank->domain, irq);
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if (!virq) {
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dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
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continue;
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}
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dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
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/*
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* Triggering IRQ on both rising and falling edge
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* needs manual intervention.
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*/
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if (bank->toggle_edge_mode & BIT(irq)) {
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u32 data, data_old, polarity;
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unsigned long flags;
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data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
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do {
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raw_spin_lock_irqsave(&bank->slock, flags);
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polarity = readl_relaxed(bank->reg_base +
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GPIO_INT_POLARITY);
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if (data & BIT(irq))
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polarity &= ~BIT(irq);
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else
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polarity |= BIT(irq);
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writel(polarity,
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bank->reg_base + GPIO_INT_POLARITY);
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raw_spin_unlock_irqrestore(&bank->slock, flags);
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data_old = data;
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data = readl_relaxed(bank->reg_base +
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GPIO_EXT_PORT);
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} while ((data & BIT(irq)) != (data_old & BIT(irq)));
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}
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generic_handle_irq(virq);
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}
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chained_irq_exit(chip, desc);
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}
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static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct rockchip_pin_bank *bank = gc->private;
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u32 mask = BIT(d->hwirq);
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u32 polarity;
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u32 level;
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u32 data;
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unsigned long flags;
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int ret;
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/* make sure the pin is configured as gpio input */
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ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
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if (ret < 0)
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return ret;
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raw_spin_lock_irqsave(&bank->slock, flags);
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data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
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data &= ~mask;
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writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
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raw_spin_unlock_irqrestore(&bank->slock, flags);
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if (type & IRQ_TYPE_EDGE_BOTH)
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irq_set_handler_locked(d, handle_edge_irq);
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else
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irq_set_handler_locked(d, handle_level_irq);
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raw_spin_lock_irqsave(&bank->slock, flags);
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irq_gc_lock(gc);
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level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
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polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
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switch (type) {
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case IRQ_TYPE_EDGE_BOTH:
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bank->toggle_edge_mode |= mask;
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level |= mask;
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/*
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* Determine gpio state. If 1 next interrupt should be falling
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* otherwise rising.
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*/
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data = readl(bank->reg_base + GPIO_EXT_PORT);
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if (data & mask)
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polarity &= ~mask;
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else
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polarity |= mask;
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break;
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case IRQ_TYPE_EDGE_RISING:
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bank->toggle_edge_mode &= ~mask;
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level |= mask;
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polarity |= mask;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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bank->toggle_edge_mode &= ~mask;
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level |= mask;
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polarity &= ~mask;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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bank->toggle_edge_mode &= ~mask;
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level &= ~mask;
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polarity |= mask;
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break;
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case IRQ_TYPE_LEVEL_LOW:
|
||||
bank->toggle_edge_mode &= ~mask;
|
||||
level &= ~mask;
|
||||
polarity &= ~mask;
|
||||
break;
|
||||
default:
|
||||
irq_gc_unlock(gc);
|
||||
raw_spin_unlock_irqrestore(&bank->slock, flags);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
|
||||
writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
|
||||
|
||||
irq_gc_unlock(gc);
|
||||
raw_spin_unlock_irqrestore(&bank->slock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void rockchip_irq_suspend(struct irq_data *d)
|
||||
{
|
||||
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
|
||||
struct rockchip_pin_bank *bank = gc->private;
|
||||
|
||||
bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
|
||||
irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
|
||||
}
|
||||
|
||||
static void rockchip_irq_resume(struct irq_data *d)
|
||||
{
|
||||
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
|
||||
struct rockchip_pin_bank *bank = gc->private;
|
||||
|
||||
irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
|
||||
}
|
||||
|
||||
static void rockchip_irq_enable(struct irq_data *d)
|
||||
{
|
||||
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
|
||||
struct rockchip_pin_bank *bank = gc->private;
|
||||
|
||||
irq_gc_mask_clr_bit(d);
|
||||
}
|
||||
|
||||
static void rockchip_irq_disable(struct irq_data *d)
|
||||
{
|
||||
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
|
||||
struct rockchip_pin_bank *bank = gc->private;
|
||||
|
||||
irq_gc_mask_set_bit(d);
|
||||
}
|
||||
|
||||
static int rockchip_interrupts_register(struct platform_device *pdev,
|
||||
struct rockchip_pinctrl *info)
|
||||
{
|
||||
struct rockchip_pin_ctrl *ctrl = info->ctrl;
|
||||
struct rockchip_pin_bank *bank = ctrl->pin_banks;
|
||||
unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
|
||||
struct irq_chip_generic *gc;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
|
||||
if (!bank->valid) {
|
||||
dev_warn(&pdev->dev, "bank %s is not valid\n",
|
||||
bank->name);
|
||||
continue;
|
||||
}
|
||||
|
||||
bank->domain = irq_domain_add_linear(bank->of_node, 32,
|
||||
&irq_generic_chip_ops, NULL);
|
||||
if (!bank->domain) {
|
||||
dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
|
||||
bank->name);
|
||||
continue;
|
||||
}
|
||||
|
||||
ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
|
||||
"rockchip_gpio_irq", handle_level_irq,
|
||||
clr, 0, 0);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
|
||||
bank->name);
|
||||
irq_domain_remove(bank->domain);
|
||||
continue;
|
||||
}
|
||||
|
||||
gc = irq_get_domain_generic_chip(bank->domain, 0);
|
||||
gc->reg_base = bank->reg_base;
|
||||
gc->private = bank;
|
||||
gc->chip_types[0].regs.mask = GPIO_INTMASK;
|
||||
gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
|
||||
gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
|
||||
gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
|
||||
gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
|
||||
gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
|
||||
gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
|
||||
gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
|
||||
gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
|
||||
gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
|
||||
gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
|
||||
gc->wake_enabled = IRQ_MSK(bank->nr_pins);
|
||||
|
||||
/*
|
||||
* Linux assumes that all interrupts start out disabled/masked.
|
||||
* Our driver only uses the concept of masked and always keeps
|
||||
* things enabled, so for us that's all masked and all enabled.
|
||||
*/
|
||||
writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
|
||||
writel_relaxed(0xffffffff, bank->reg_base + GPIO_PORTS_EOI);
|
||||
writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
|
||||
gc->mask_cache = 0xffffffff;
|
||||
|
||||
irq_set_chained_handler_and_data(bank->irq,
|
||||
rockchip_irq_demux, bank);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rockchip_gpiolib_register(struct platform_device *pdev,
|
||||
struct rockchip_pinctrl *info)
|
||||
{
|
||||
struct rockchip_pin_ctrl *ctrl = info->ctrl;
|
||||
struct rockchip_pin_bank *bank = ctrl->pin_banks;
|
||||
struct gpio_chip *gc;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
|
||||
if (!bank->valid) {
|
||||
dev_warn(&pdev->dev, "bank %s is not valid\n",
|
||||
bank->name);
|
||||
continue;
|
||||
}
|
||||
|
||||
bank->gpio_chip = rockchip_gpiolib_chip;
|
||||
|
||||
gc = &bank->gpio_chip;
|
||||
gc->base = bank->pin_base;
|
||||
gc->ngpio = bank->nr_pins;
|
||||
gc->parent = &pdev->dev;
|
||||
gc->of_node = bank->of_node;
|
||||
gc->label = bank->name;
|
||||
|
||||
ret = gpiochip_add_data(gc, bank);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
|
||||
gc->label, ret);
|
||||
goto fail;
|
||||
}
|
||||
}
|
||||
|
||||
rockchip_interrupts_register(pdev, info);
|
||||
|
||||
return 0;
|
||||
|
||||
fail:
|
||||
for (--i, --bank; i >= 0; --i, --bank) {
|
||||
if (!bank->valid)
|
||||
continue;
|
||||
gpiochip_remove(&bank->gpio_chip);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rockchip_gpiolib_unregister(struct platform_device *pdev,
|
||||
struct rockchip_pinctrl *info)
|
||||
{
|
||||
struct rockchip_pin_ctrl *ctrl = info->ctrl;
|
||||
struct rockchip_pin_bank *bank = ctrl->pin_banks;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
|
||||
if (!bank->valid)
|
||||
continue;
|
||||
gpiochip_remove(&bank->gpio_chip);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
|
||||
struct rockchip_pinctrl *info)
|
||||
{
|
||||
struct resource res;
|
||||
void __iomem *base;
|
||||
|
||||
if (of_address_to_resource(bank->of_node, 0, &res)) {
|
||||
dev_err(info->dev, "cannot find IO resource for bank\n");
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
bank->reg_base = devm_ioremap_resource(info->dev, &res);
|
||||
if (IS_ERR(bank->reg_base))
|
||||
return PTR_ERR(bank->reg_base);
|
||||
|
||||
/*
|
||||
* special case, where parts of the pull setting-registers are
|
||||
* part of the PMU register space
|
||||
*/
|
||||
if (of_device_is_compatible(bank->of_node,
|
||||
"rockchip,rk3188-gpio-bank0")) {
|
||||
struct device_node *node;
|
||||
|
||||
node = of_parse_phandle(bank->of_node->parent,
|
||||
"rockchip,pmu", 0);
|
||||
if (!node) {
|
||||
if (of_address_to_resource(bank->of_node, 1, &res)) {
|
||||
dev_err(info->dev, "cannot find IO resource for bank\n");
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
base = devm_ioremap_resource(info->dev, &res);
|
||||
if (IS_ERR(base))
|
||||
return PTR_ERR(base);
|
||||
rockchip_regmap_config.max_register =
|
||||
resource_size(&res) - 4;
|
||||
rockchip_regmap_config.name =
|
||||
"rockchip,rk3188-gpio-bank0-pull";
|
||||
bank->regmap_pull = devm_regmap_init_mmio(info->dev,
|
||||
base,
|
||||
&rockchip_regmap_config);
|
||||
}
|
||||
of_node_put(node);
|
||||
}
|
||||
|
||||
bank->irq = irq_of_parse_and_map(bank->of_node, 0);
|
||||
|
||||
bank->clk = of_clk_get(bank->of_node, 0);
|
||||
if (IS_ERR(bank->clk))
|
||||
return PTR_ERR(bank->clk);
|
||||
|
||||
return clk_prepare_enable(bank->clk);
|
||||
}
|
||||
|
||||
static const struct of_device_id rockchip_pinctrl_dt_match[];
|
||||
|
||||
/* retrieve the soc specific data */
|
||||
@ -3067,7 +2474,6 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
|
||||
{
|
||||
const struct of_device_id *match;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
struct device_node *np;
|
||||
struct rockchip_pin_ctrl *ctrl;
|
||||
struct rockchip_pin_bank *bank;
|
||||
int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
|
||||
@ -3075,23 +2481,6 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
|
||||
match = of_match_node(rockchip_pinctrl_dt_match, node);
|
||||
ctrl = (struct rockchip_pin_ctrl *)match->data;
|
||||
|
||||
for_each_child_of_node(node, np) {
|
||||
if (!of_find_property(np, "gpio-controller", NULL))
|
||||
continue;
|
||||
|
||||
bank = ctrl->pin_banks;
|
||||
for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
|
||||
if (!strcmp(bank->name, np->name)) {
|
||||
bank->of_node = np;
|
||||
|
||||
if (!rockchip_get_bank_data(bank, d))
|
||||
bank->valid = true;
|
||||
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
grf_offs = ctrl->grf_mux_offset;
|
||||
pmu_offs = ctrl->pmu_mux_offset;
|
||||
drv_pmu_offs = ctrl->pmu_drv_offset;
|
||||
@ -3312,18 +2701,18 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev)
|
||||
return PTR_ERR(info->regmap_pmu);
|
||||
}
|
||||
|
||||
ret = rockchip_gpiolib_register(pdev, info);
|
||||
ret = rockchip_pinctrl_register(pdev, info);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = rockchip_pinctrl_register(pdev, info);
|
||||
platform_set_drvdata(pdev, info);
|
||||
|
||||
ret = of_platform_populate(np, rockchip_bank_match, NULL, NULL);
|
||||
if (ret) {
|
||||
rockchip_gpiolib_unregister(pdev, info);
|
||||
dev_err(&pdev->dev, "failed to register gpio device\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, info);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user