clk: qcom: ipq8074: add PCIE, USB and SDCC clocks

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- It has 2 instances of PCIE which uses AXI, AHB, AUX, SYS NOC
  AXI and PIPE clocks.
- It has 2 instances of USB 3.0 which uses AUX, SLEEP, PIPE,
  SYS NOC, mock UTMI and master clocks.
- It has 2 instances of SDCC which uses APSS and AHB clock.
  SDCC1 requires ICE core clock also.
- All the PIPE clocks are external clocks which will be
  registered in clock framework by PHY drivers. The enabling
  and disabling of PIPE RCG clocks are dependent upon PHY
  initialization sequence so BRANCH_HALT_DELAY flag is required for
  these clocks.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

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Abhishek Sahu 2017-12-13 19:55:37 +05:30 committed by Stephen Boyd

parent b8e7e51962

commit 9607f6224b

1 changed files with 994 additions and 0 deletions

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drivers/clk/qcom/gcc-ipq8074.c

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