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drm/amd/display: update dml to rev.99 and smu clk_table w/a

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[why]
1. update dml to rev.99
2. add smu clk table w/a: smu gives 1 dtm level with mismatch votage
   table which causes multiple issues.

Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Charlene Liu 2022-01-07 04:46:36 -05:00 committed by Alex Deucher
parent 58c69b53ae
commit 9338cb719f
2 changed files with 28 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
View File

@ -64,6 +64,8 @@ typedef struct {
double DCFCLKDeepSleep;
unsigned int DPPPerPlane;
bool ScalerEnabled;
double VRatio;
double VRatioChroma;
enum scan_direction_class SourceScan;
unsigned int BlockWidth256BytesY;
unsigned int BlockHeight256BytesY;
@ -942,6 +944,7 @@ static bool CalculatePrefetchSchedule(
double dst_y_prefetch_equ;
double Tsw_oto;
double prefetch_bw_oto;
double prefetch_bw_pr;
double Tvm_oto;
double Tr0_oto;
double Tvm_oto_lines;
@ -971,6 +974,7 @@ static bool CalculatePrefetchSchedule(
double min_Lsw;
double Tsw_est1 = 0;
double Tsw_est3 = 0;
double max_Tsw = 0;
if (GPUVMEnable == true && HostVMEnable == true) {
HostVMDynamicLevelsTrips = HostVMMaxNonCachedPageTableLevels;
@ -1111,11 +1115,14 @@ static bool CalculatePrefetchSchedule(
bytes_pp = myPipe->BytePerPixelY + myPipe->BytePerPixelC / 4;
else
bytes_pp = myPipe->BytePerPixelY + myPipe->BytePerPixelC;
/*rev 99*/
prefetch_bw_pr = dml_min(1, bytes_pp * myPipe->PixelClock / (double) myPipe->DPPPerPlane);
max_Tsw = dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) * LineTime;
prefetch_sw_bytes = PrefetchSourceLinesY * swath_width_luma_ub * myPipe->BytePerPixelY + PrefetchSourceLinesC * swath_width_chroma_ub * myPipe->BytePerPixelC;
prefetch_bw_oto = dml_max(bytes_pp * myPipe->PixelClock / myPipe->DPPPerPlane, prefetch_sw_bytes / (dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) * LineTime));
prefetch_bw_oto = dml_max(prefetch_bw_pr, prefetch_sw_bytes / max_Tsw);
min_Lsw = dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) / max_vratio_pre;
min_Lsw = dml_max(1, dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) / max_vratio_pre);
Lsw_oto = dml_ceil(4 * dml_max(prefetch_sw_bytes / prefetch_bw_oto / LineTime, min_Lsw), 1) / 4;
Tsw_oto = Lsw_oto * LineTime;
@ -1389,7 +1396,7 @@ static bool CalculatePrefetchSchedule(
dml_print("DML::%s: SwathHeightC = %d\n", __func__, SwathHeightC);
dml_print("DML::%s: VInitPreFillC = %f\n", __func__, VInitPreFillC);
#endif
if ((SwathHeightC > 4)) {
if ((SwathHeightC > 4) || VInitPreFillC > 3) {
if (LinesToRequestPrefetchPixelData > (VInitPreFillC - 3.0) / 2.0) {
*VRatioPrefetchC = dml_max(
*VRatioPrefetchC,
@ -2663,6 +2670,8 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
myPipe.DCFCLKDeepSleep = v->DCFCLKDeepSleep;
myPipe.DPPPerPlane = v->DPPPerPlane[k];
myPipe.ScalerEnabled = v->ScalerEnabled[k];
myPipe.VRatio = v->VRatio[k];
myPipe.VRatioChroma = v->VRatioChroma[k];
myPipe.SourceScan = v->SourceScan[k];
myPipe.BlockWidth256BytesY = v->BlockWidth256BytesY[k];
myPipe.BlockHeight256BytesY = v->BlockHeight256BytesY[k];
@ -3911,6 +3920,9 @@ static noinline void CalculatePrefetchSchedulePerPlane(
myPipe.DCFCLKDeepSleep = v->ProjectedDCFCLKDeepSleep[i][j];
myPipe.DPPPerPlane = v->NoOfDPP[i][j][k];
myPipe.ScalerEnabled = v->ScalerEnabled[k];
myPipe.VRatio = mode_lib->vba.VRatio[k];
myPipe.VRatioChroma = mode_lib->vba.VRatioChroma[k];
myPipe.SourceScan = v->SourceScan[k];
myPipe.BlockWidth256BytesY = v->Read256BlockWidthY[k];
myPipe.BlockHeight256BytesY = v->Read256BlockHeightY[k];
@ -4987,6 +4999,17 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
&v->meta_row_bandwidth[i][j][k],
&v->dpte_row_bandwidth[i][j][k]);
}
/*DCCMetaBufferSizeSupport(i, j) = True
For k = 0 To NumberOfActivePlanes - 1
If MetaRowBytes(i, j, k) > 24064 Then
DCCMetaBufferSizeSupport(i, j) = False
End If
Next k*/
v->DCCMetaBufferSizeSupport[i][j] = true;
for (k = 0; k < v->NumberOfActivePlanes; ++k) {
if (v->MetaRowBytes[i][j][k] > 24064)
v->DCCMetaBufferSizeSupport[i][j] = false;
}
v->UrgLatency[i] = CalculateUrgentLatency(
v->UrgentLatencyPixelDataOnly,
v->UrgentLatencyPixelMixedWithVMData,

2
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
View File

@ -544,6 +544,8 @@ struct vba_vars_st {
bool DTBCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES];
double UrgentRoundTripAndOutOfOrderLatencyPerState[DC__VOLTAGE_STATES];
bool ROBSupport[DC__VOLTAGE_STATES][2];
//based on rev 99: Dim DCCMetaBufferSizeSupport(NumberOfStates, 1) As Boolean
bool DCCMetaBufferSizeSupport[DC__VOLTAGE_STATES][2];
bool PTEBufferSizeNotExceeded[DC__VOLTAGE_STATES][2];
bool TotalVerticalActiveBandwidthSupport[DC__VOLTAGE_STATES][2];
double MaxTotalVerticalActiveAvailableBandwidth[DC__VOLTAGE_STATES][2];