staging iio: lis3l02dq cleanup
fixes some typos, whitespace, comments Signed-off-by: Peter Meerwald <pmeerw@pmeerw.net> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
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@ -28,7 +28,7 @@
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/* Control Register (1 of 2) */
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#define LIS3L02DQ_REG_CTRL_1_ADDR 0x20
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/* Power ctrl - either bit set corresponds to on*/
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#define LIS3L02DQ_REG_CTRL_1_PD_ON 0xC0
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#define LIS3L02DQ_REG_CTRL_1_PD_ON 0xC0
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/* Decimation Factor */
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#define LIS3L02DQ_DEC_MASK 0x30
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@ -73,14 +73,14 @@
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/* Interrupt related stuff */
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#define LIS3L02DQ_REG_WAKE_UP_CFG_ADDR 0x23
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/* Switch from or combination fo conditions to and */
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/* Switch from or combination of conditions to and */
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#define LIS3L02DQ_REG_WAKE_UP_CFG_BOOLEAN_AND 0x80
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/* Latch interrupt request,
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* if on ack must be given by reading the ack register */
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#define LIS3L02DQ_REG_WAKE_UP_CFG_LATCH_SRC 0x40
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/* Z Interrupt on High (above threshold)*/
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/* Z Interrupt on High (above threshold) */
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#define LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_Z_HIGH 0x20
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/* Z Interrupt on Low */
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#define LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_Z_LOW 0x10
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@ -117,13 +117,13 @@
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#define LIS3L02DQ_REG_STATUS_Y_OVERRUN 0x20
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#define LIS3L02DQ_REG_STATUS_X_OVERRUN 0x10
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/* XYZ new data available - first is all 3 available? */
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#define LIS3L02DQ_REG_STATUS_XYZ_NEW_DATA 0x08
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#define LIS3L02DQ_REG_STATUS_XYZ_NEW_DATA 0x08
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#define LIS3L02DQ_REG_STATUS_Z_NEW_DATA 0x04
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#define LIS3L02DQ_REG_STATUS_Y_NEW_DATA 0x02
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#define LIS3L02DQ_REG_STATUS_X_NEW_DATA 0x01
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/* The accelerometer readings - low and high bytes.
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Form of high byte dependent on justification set in ctrl reg */
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* Form of high byte dependent on justification set in ctrl reg */
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#define LIS3L02DQ_REG_OUT_X_L_ADDR 0x28
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#define LIS3L02DQ_REG_OUT_X_H_ADDR 0x29
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#define LIS3L02DQ_REG_OUT_Y_L_ADDR 0x2A
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@ -150,9 +150,9 @@ Form of high byte dependent on justification set in ctrl reg */
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* struct lis3l02dq_state - device instance specific data
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* @us: actual spi_device
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* @trig: data ready trigger registered with iio
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* @buf_lock: mutex to protect tx and rx
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* @tx: transmit buffer
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* @rx: receive buffer
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* @buf_lock: mutex to protect tx and rx
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**/
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struct lis3l02dq_state {
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struct spi_device *us;
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@ -392,7 +392,7 @@ static int lis3l02dq_initial_setup(struct iio_dev *indio_dev)
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dev_err(&st->us->dev, "problem with setup control register 1");
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goto err_ret;
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}
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/* Repeat as sometimes doesn't work first time?*/
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/* Repeat as sometimes doesn't work first time? */
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ret = lis3l02dq_spi_write_reg_8(indio_dev,
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LIS3L02DQ_REG_CTRL_1_ADDR,
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val);
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@ -686,7 +686,7 @@ static int __devinit lis3l02dq_probe(struct spi_device *spi)
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goto error_ret;
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}
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st = iio_priv(indio_dev);
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/* this is only used tor removal purposes */
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/* this is only used for removal purposes */
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spi_set_drvdata(spi, indio_dev);
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st->us = spi;
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@ -14,7 +14,7 @@
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#include "lis3l02dq.h"
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/**
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* combine_8_to_16() utility function to munge to u8s into u16
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* combine_8_to_16() utility function to munge two u8s into u16
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**/
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static inline u16 combine_8_to_16(u8 lower, u8 upper)
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{
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@ -49,7 +49,7 @@ static const u8 read_all_tx_array[] = {
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/**
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* lis3l02dq_read_all() Reads all channels currently selected
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* @st: device specific state
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* @indio_dev: IIO device state
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* @rx_array: (dma capable) receive array, must be at least
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* 4*number of channels
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**/
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@ -170,22 +170,22 @@ __lis3l02dq_write_data_ready_config(struct iio_dev *indio_dev, bool state)
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bool currentlyset;
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struct lis3l02dq_state *st = iio_priv(indio_dev);
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/* Get the current event mask register */
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/* Get the current event mask register */
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ret = lis3l02dq_spi_read_reg_8(indio_dev,
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LIS3L02DQ_REG_CTRL_2_ADDR,
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&valold);
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if (ret)
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goto error_ret;
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/* Find out if data ready is already on */
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/* Find out if data ready is already on */
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currentlyset
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= valold & LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;
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/* Disable requested */
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/* Disable requested */
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if (!state && currentlyset) {
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/* disable the data ready signal */
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/* Disable the data ready signal */
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valold &= ~LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;
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/* The double write is to overcome a hardware bug?*/
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/* The double write is to overcome a hardware bug? */
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ret = lis3l02dq_spi_write_reg_8(indio_dev,
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LIS3L02DQ_REG_CTRL_2_ADDR,
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valold);
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@ -197,10 +197,10 @@ __lis3l02dq_write_data_ready_config(struct iio_dev *indio_dev, bool state)
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if (ret)
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goto error_ret;
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st->trigger_on = false;
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/* Enable requested */
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/* Enable requested */
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} else if (state && !currentlyset) {
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/* if not set, enable requested */
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/* first disable all events */
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/* If not set, enable requested
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* first disable all events */
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ret = lis3l02dq_disable_all_events(indio_dev);
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if (ret < 0)
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goto error_ret;
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@ -239,7 +239,7 @@ static int lis3l02dq_data_rdy_trigger_set_state(struct iio_trigger *trig,
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if (state == false) {
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/*
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* A possible quirk with the handler is currently worked around
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* by ensuring outstanding read events are cleared.
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* by ensuring outstanding read events are cleared.
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*/
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ret = lis3l02dq_read_all(indio_dev, NULL);
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}
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@ -250,7 +250,7 @@ static int lis3l02dq_data_rdy_trigger_set_state(struct iio_trigger *trig,
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}
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/**
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* lis3l02dq_trig_try_reen() try renabling irq for data rdy trigger
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* lis3l02dq_trig_try_reen() try reenabling irq for data rdy trigger
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* @trig: the datardy trigger
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*/
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static int lis3l02dq_trig_try_reen(struct iio_trigger *trig)
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@ -259,8 +259,8 @@ static int lis3l02dq_trig_try_reen(struct iio_trigger *trig)
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struct lis3l02dq_state *st = iio_priv(indio_dev);
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int i;
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/* If gpio still high (or high again) */
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/* In theory possible we will need to do this several times */
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/* If gpio still high (or high again)
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* In theory possible we will need to do this several times */
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for (i = 0; i < 5; i++)
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if (gpio_get_value(irq_to_gpio(st->us->irq)))
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lis3l02dq_read_all(indio_dev, NULL);
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