liquidio CN23XX: init VF softcommand queues
Adds support for initializing softcommand, dispatch and instructions queues for VF. Signed-off-by: Raghu Vatsavayi <raghu.vatsavayi@caviumnetworks.com> Signed-off-by: Derek Chickles <derek.chickles@caviumnetworks.com> Signed-off-by: Satanand Burla <satananda.burla@caviumnetworks.com> Signed-off-by: Felix Manlunas <felix.manlunas@caviumnetworks.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -140,7 +140,40 @@ static void octeon_pci_flr(struct octeon_device *oct)
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*/
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*/
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static void octeon_destroy_resources(struct octeon_device *oct)
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static void octeon_destroy_resources(struct octeon_device *oct)
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{
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{
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int i;
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switch (atomic_read(&oct->status)) {
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switch (atomic_read(&oct->status)) {
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case OCT_DEV_IN_RESET:
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case OCT_DEV_DROQ_INIT_DONE:
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mdelay(100);
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for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct); i++) {
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if (!(oct->io_qmask.oq & BIT_ULL(i)))
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continue;
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octeon_delete_droq(oct, i);
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}
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/* fallthrough */
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case OCT_DEV_RESP_LIST_INIT_DONE:
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octeon_delete_response_list(oct);
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/* fallthrough */
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case OCT_DEV_INSTR_QUEUE_INIT_DONE:
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for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct); i++) {
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if (!(oct->io_qmask.iq & BIT_ULL(i)))
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continue;
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octeon_delete_instr_queue(oct, i);
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}
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/* fallthrough */
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case OCT_DEV_SC_BUFF_POOL_INIT_DONE:
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octeon_free_sc_buffer_pool(oct);
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/* fallthrough */
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case OCT_DEV_DISPATCH_INIT_DONE:
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octeon_delete_dispatch_list(oct);
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cancel_delayed_work_sync(&oct->nic_poll_work.work);
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/* fallthrough */
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case OCT_DEV_PCI_MAP_DONE:
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case OCT_DEV_PCI_MAP_DONE:
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octeon_unmap_pci_barx(oct, 0);
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octeon_unmap_pci_barx(oct, 0);
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octeon_unmap_pci_barx(oct, 1);
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octeon_unmap_pci_barx(oct, 1);
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@ -236,6 +269,14 @@ static int octeon_device_init(struct octeon_device *oct)
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atomic_set(&oct->status, OCT_DEV_PCI_MAP_DONE);
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atomic_set(&oct->status, OCT_DEV_PCI_MAP_DONE);
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/* Initialize the dispatch mechanism used to push packets arriving on
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* Octeon Output queues.
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*/
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if (octeon_init_dispatch_list(oct))
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return 1;
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atomic_set(&oct->status, OCT_DEV_DISPATCH_INIT_DONE);
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if (octeon_set_io_queues_off(oct)) {
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if (octeon_set_io_queues_off(oct)) {
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dev_err(&oct->pci_dev->dev, "setting io queues off failed\n");
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dev_err(&oct->pci_dev->dev, "setting io queues off failed\n");
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return 1;
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return 1;
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@ -246,6 +287,35 @@ static int octeon_device_init(struct octeon_device *oct)
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return 1;
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return 1;
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}
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}
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/* Initialize soft command buffer pool */
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if (octeon_setup_sc_buffer_pool(oct)) {
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dev_err(&oct->pci_dev->dev, "sc buffer pool allocation failed\n");
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return 1;
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}
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atomic_set(&oct->status, OCT_DEV_SC_BUFF_POOL_INIT_DONE);
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/* Setup the data structures that manage this Octeon's Input queues. */
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if (octeon_setup_instr_queues(oct)) {
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dev_err(&oct->pci_dev->dev, "instruction queue initialization failed\n");
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return 1;
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}
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atomic_set(&oct->status, OCT_DEV_INSTR_QUEUE_INIT_DONE);
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/* Initialize lists to manage the requests of different types that
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* arrive from user & kernel applications for this octeon device.
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*/
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if (octeon_setup_response_list(oct)) {
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dev_err(&oct->pci_dev->dev, "Response list allocation failed\n");
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return 1;
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}
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atomic_set(&oct->status, OCT_DEV_RESP_LIST_INIT_DONE);
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if (octeon_setup_output_queues(oct)) {
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dev_err(&oct->pci_dev->dev, "Output queue initialization failed\n");
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return 1;
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}
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atomic_set(&oct->status, OCT_DEV_DROQ_INIT_DONE);
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return 0;
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return 0;
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}
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}
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@ -797,6 +797,8 @@ int octeon_setup_instr_queues(struct octeon_device *oct)
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CFG_GET_NUM_DEF_TX_DESCS(CHIP_CONF(oct, cn6xxx));
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CFG_GET_NUM_DEF_TX_DESCS(CHIP_CONF(oct, cn6xxx));
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else if (OCTEON_CN23XX_PF(oct))
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else if (OCTEON_CN23XX_PF(oct))
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num_descs = CFG_GET_NUM_DEF_TX_DESCS(CHIP_CONF(oct, cn23xx_pf));
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num_descs = CFG_GET_NUM_DEF_TX_DESCS(CHIP_CONF(oct, cn23xx_pf));
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else if (OCTEON_CN23XX_VF(oct))
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num_descs = CFG_GET_NUM_DEF_TX_DESCS(CHIP_CONF(oct, cn23xx_vf));
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oct->num_iqs = 0;
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oct->num_iqs = 0;
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@ -842,6 +844,9 @@ int octeon_setup_output_queues(struct octeon_device *oct)
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} else if (OCTEON_CN23XX_PF(oct)) {
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} else if (OCTEON_CN23XX_PF(oct)) {
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num_descs = CFG_GET_NUM_DEF_RX_DESCS(CHIP_CONF(oct, cn23xx_pf));
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num_descs = CFG_GET_NUM_DEF_RX_DESCS(CHIP_CONF(oct, cn23xx_pf));
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desc_size = CFG_GET_DEF_RX_BUF_SIZE(CHIP_CONF(oct, cn23xx_pf));
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desc_size = CFG_GET_DEF_RX_BUF_SIZE(CHIP_CONF(oct, cn23xx_pf));
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} else if (OCTEON_CN23XX_VF(oct)) {
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num_descs = CFG_GET_NUM_DEF_RX_DESCS(CHIP_CONF(oct, cn23xx_vf));
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desc_size = CFG_GET_DEF_RX_BUF_SIZE(CHIP_CONF(oct, cn23xx_vf));
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}
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}
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oct->num_oqs = 0;
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oct->num_oqs = 0;
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oct->droq[0] = vmalloc_node(sizeof(*oct->droq[0]), numa_node);
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oct->droq[0] = vmalloc_node(sizeof(*oct->droq[0]), numa_node);
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@ -28,6 +28,7 @@
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#include "octeon_network.h"
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#include "octeon_network.h"
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#include "cn66xx_device.h"
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#include "cn66xx_device.h"
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#include "cn23xx_pf_device.h"
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#include "cn23xx_pf_device.h"
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#include "cn23xx_vf_device.h"
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struct iq_post_status {
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struct iq_post_status {
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int status;
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int status;
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@ -68,6 +69,9 @@ int octeon_init_instr_queue(struct octeon_device *oct,
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conf = &(CFG_GET_IQ_CFG(CHIP_CONF(oct, cn6xxx)));
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conf = &(CFG_GET_IQ_CFG(CHIP_CONF(oct, cn6xxx)));
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else if (OCTEON_CN23XX_PF(oct))
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else if (OCTEON_CN23XX_PF(oct))
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conf = &(CFG_GET_IQ_CFG(CHIP_CONF(oct, cn23xx_pf)));
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conf = &(CFG_GET_IQ_CFG(CHIP_CONF(oct, cn23xx_pf)));
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else if (OCTEON_CN23XX_VF(oct))
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conf = &(CFG_GET_IQ_CFG(CHIP_CONF(oct, cn23xx_vf)));
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if (!conf) {
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if (!conf) {
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dev_err(&oct->pci_dev->dev, "Unsupported Chip %x\n",
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dev_err(&oct->pci_dev->dev, "Unsupported Chip %x\n",
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oct->chip_id);
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oct->chip_id);
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@ -183,6 +187,9 @@ int octeon_delete_instr_queue(struct octeon_device *oct, u32 iq_no)
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else if (OCTEON_CN23XX_PF(oct))
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else if (OCTEON_CN23XX_PF(oct))
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desc_size =
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desc_size =
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CFG_GET_IQ_INSTR_TYPE(CHIP_CONF(oct, cn23xx_pf));
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CFG_GET_IQ_INSTR_TYPE(CHIP_CONF(oct, cn23xx_pf));
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else if (OCTEON_CN23XX_VF(oct))
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desc_size =
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CFG_GET_IQ_INSTR_TYPE(CHIP_CONF(oct, cn23xx_vf));
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vfree(iq->request_list);
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vfree(iq->request_list);
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