liquidio CN23XX: VF register access
This patch adds support for VF device register access. Signed-off-by: Raghu Vatsavayi <raghu.vatsavayi@caviumnetworks.com> Signed-off-by: Derek Chickles <derek.chickles@caviumnetworks.com> Signed-off-by: Satanand Burla <satananda.burla@caviumnetworks.com> Signed-off-by: Felix Manlunas <felix.manlunas@caviumnetworks.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Raghu Vatsavayi
David S. Miller
parent
c865cdf13a
commit
da15c78b56
@ -76,6 +76,161 @@ static int cn23xx_vf_reset_io_queues(struct octeon_device *oct, u32 num_queues)
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return ret_val;
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}
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static int cn23xx_vf_setup_global_input_regs(struct octeon_device *oct)
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{
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struct octeon_cn23xx_vf *cn23xx = (struct octeon_cn23xx_vf *)oct->chip;
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struct octeon_instr_queue *iq;
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u64 q_no, intr_threshold;
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u64 d64;
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if (cn23xx_vf_reset_io_queues(oct, oct->sriov_info.rings_per_vf))
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return -1;
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for (q_no = 0; q_no < (oct->sriov_info.rings_per_vf); q_no++) {
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void __iomem *inst_cnt_reg;
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octeon_write_csr64(oct, CN23XX_VF_SLI_IQ_DOORBELL(q_no),
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0xFFFFFFFF);
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iq = oct->instr_queue[q_no];
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if (iq)
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inst_cnt_reg = iq->inst_cnt_reg;
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else
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inst_cnt_reg = (u8 *)oct->mmio[0].hw_addr +
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CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no);
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d64 = octeon_read_csr64(oct,
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CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no));
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d64 &= 0xEFFFFFFFFFFFFFFFL;
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octeon_write_csr64(oct, CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no),
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d64);
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/* Select ES, RO, NS, RDSIZE,DPTR Fomat#0 for
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* the Input Queues
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*/
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octeon_write_csr64(oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no),
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CN23XX_PKT_INPUT_CTL_MASK);
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/* set the wmark level to trigger PI_INT */
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intr_threshold = CFG_GET_IQ_INTR_PKT(cn23xx->conf) &
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CN23XX_PKT_IN_DONE_WMARK_MASK;
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writeq((readq(inst_cnt_reg) &
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~(CN23XX_PKT_IN_DONE_WMARK_MASK <<
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CN23XX_PKT_IN_DONE_WMARK_BIT_POS)) |
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(intr_threshold << CN23XX_PKT_IN_DONE_WMARK_BIT_POS),
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inst_cnt_reg);
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}
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return 0;
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}
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static void cn23xx_vf_setup_global_output_regs(struct octeon_device *oct)
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{
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u32 reg_val;
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u32 q_no;
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for (q_no = 0; q_no < (oct->sriov_info.rings_per_vf); q_no++) {
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octeon_write_csr(oct, CN23XX_VF_SLI_OQ_PKTS_CREDIT(q_no),
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0xFFFFFFFF);
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reg_val =
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octeon_read_csr(oct, CN23XX_VF_SLI_OQ_PKTS_SENT(q_no));
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reg_val &= 0xEFFFFFFFFFFFFFFFL;
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reg_val =
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octeon_read_csr(oct, CN23XX_VF_SLI_OQ_PKT_CONTROL(q_no));
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/* set IPTR & DPTR */
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reg_val |=
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(CN23XX_PKT_OUTPUT_CTL_IPTR | CN23XX_PKT_OUTPUT_CTL_DPTR);
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/* reset BMODE */
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reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_BMODE);
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/* No Relaxed Ordering, No Snoop, 64-bit Byte swap
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* for Output Queue ScatterList reset ROR_P, NSR_P
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*/
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reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR_P);
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reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR_P);
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#ifdef __LITTLE_ENDIAN_BITFIELD
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reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ES_P);
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#else
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reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES_P);
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#endif
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/* No Relaxed Ordering, No Snoop, 64-bit Byte swap
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* for Output Queue Data reset ROR, NSR
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*/
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reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR);
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reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR);
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/* set the ES bit */
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reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES);
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/* write all the selected settings */
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octeon_write_csr(oct, CN23XX_VF_SLI_OQ_PKT_CONTROL(q_no),
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reg_val);
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}
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}
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static int cn23xx_setup_vf_device_regs(struct octeon_device *oct)
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{
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if (cn23xx_vf_setup_global_input_regs(oct))
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return -1;
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cn23xx_vf_setup_global_output_regs(oct);
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return 0;
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}
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static void cn23xx_setup_vf_iq_regs(struct octeon_device *oct, u32 iq_no)
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{
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struct octeon_instr_queue *iq = oct->instr_queue[iq_no];
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u64 pkt_in_done;
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/* Write the start of the input queue's ring and its size */
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octeon_write_csr64(oct, CN23XX_VF_SLI_IQ_BASE_ADDR64(iq_no),
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iq->base_addr_dma);
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octeon_write_csr(oct, CN23XX_VF_SLI_IQ_SIZE(iq_no), iq->max_count);
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/* Remember the doorbell & instruction count register addr
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* for this queue
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*/
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iq->doorbell_reg =
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(u8 *)oct->mmio[0].hw_addr + CN23XX_VF_SLI_IQ_DOORBELL(iq_no);
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iq->inst_cnt_reg =
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(u8 *)oct->mmio[0].hw_addr + CN23XX_VF_SLI_IQ_INSTR_COUNT64(iq_no);
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dev_dbg(&oct->pci_dev->dev, "InstQ[%d]:dbell reg @ 0x%p instcnt_reg @ 0x%p\n",
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iq_no, iq->doorbell_reg, iq->inst_cnt_reg);
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/* Store the current instruction counter (used in flush_iq
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* calculation)
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*/
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pkt_in_done = readq(iq->inst_cnt_reg);
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iq->reset_instr_cnt = 0;
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}
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static void cn23xx_setup_vf_oq_regs(struct octeon_device *oct, u32 oq_no)
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{
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struct octeon_droq *droq = oct->droq[oq_no];
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octeon_write_csr64(oct, CN23XX_VF_SLI_OQ_BASE_ADDR64(oq_no),
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droq->desc_ring_dma);
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octeon_write_csr(oct, CN23XX_VF_SLI_OQ_SIZE(oq_no), droq->max_count);
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octeon_write_csr(oct, CN23XX_VF_SLI_OQ_BUFF_INFO_SIZE(oq_no),
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(droq->buffer_size | (OCT_RH_SIZE << 16)));
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/* Get the mapped address of the pkt_sent and pkts_credit regs */
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droq->pkts_sent_reg =
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(u8 *)oct->mmio[0].hw_addr + CN23XX_VF_SLI_OQ_PKTS_SENT(oq_no);
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droq->pkts_credit_reg =
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(u8 *)oct->mmio[0].hw_addr + CN23XX_VF_SLI_OQ_PKTS_CREDIT(oq_no);
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}
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static int cn23xx_enable_vf_io_queues(struct octeon_device *oct)
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{
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u32 q_no;
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@ -181,8 +336,42 @@ int cn23xx_setup_octeon_vf_device(struct octeon_device *oct)
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}
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}
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oct->fn_list.setup_iq_regs = cn23xx_setup_vf_iq_regs;
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oct->fn_list.setup_oq_regs = cn23xx_setup_vf_oq_regs;
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oct->fn_list.setup_device_regs = cn23xx_setup_vf_device_regs;
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oct->fn_list.enable_io_queues = cn23xx_enable_vf_io_queues;
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oct->fn_list.disable_io_queues = cn23xx_disable_vf_io_queues;
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return 0;
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}
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void cn23xx_dump_vf_iq_regs(struct octeon_device *oct)
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{
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u32 regval, q_no;
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dev_dbg(&oct->pci_dev->dev, "SLI_IQ_DOORBELL_0 [0x%x]: 0x%016llx\n",
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CN23XX_VF_SLI_IQ_DOORBELL(0),
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CVM_CAST64(octeon_read_csr64(
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oct, CN23XX_VF_SLI_IQ_DOORBELL(0))));
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dev_dbg(&oct->pci_dev->dev, "SLI_IQ_BASEADDR_0 [0x%x]: 0x%016llx\n",
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CN23XX_VF_SLI_IQ_BASE_ADDR64(0),
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CVM_CAST64(octeon_read_csr64(
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oct, CN23XX_VF_SLI_IQ_BASE_ADDR64(0))));
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dev_dbg(&oct->pci_dev->dev, "SLI_IQ_FIFO_RSIZE_0 [0x%x]: 0x%016llx\n",
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CN23XX_VF_SLI_IQ_SIZE(0),
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CVM_CAST64(octeon_read_csr64(oct, CN23XX_VF_SLI_IQ_SIZE(0))));
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for (q_no = 0; q_no < oct->sriov_info.rings_per_vf; q_no++) {
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dev_dbg(&oct->pci_dev->dev, "SLI_PKT[%d]_INPUT_CTL [0x%x]: 0x%016llx\n",
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q_no, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no),
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CVM_CAST64(octeon_read_csr64(
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oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no))));
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}
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pci_read_config_dword(oct->pci_dev, CN23XX_CONFIG_PCIE_DEVCTL, ®val);
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dev_dbg(&oct->pci_dev->dev, "Config DevCtl [0x%x]: 0x%08x\n",
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CN23XX_CONFIG_PCIE_DEVCTL, regval);
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}
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@ -35,4 +35,6 @@ struct octeon_cn23xx_vf {
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#define BUSY_READING_REG_VF_LOOP_COUNT 10000
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int cn23xx_setup_octeon_vf_device(struct octeon_device *oct);
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void cn23xx_dump_vf_initialized_regs(struct octeon_device *oct);
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#endif
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@ -241,6 +241,11 @@ static int octeon_device_init(struct octeon_device *oct)
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return 1;
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}
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if (oct->fn_list.setup_device_regs(oct)) {
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dev_err(&oct->pci_dev->dev, "device registers configuration failed\n");
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return 1;
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}
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return 0;
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}
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