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drm/nouveau/gr: switch to instanced constructor

Browse Source 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
This commit is contained in:
Ben Skeggs 2020-12-04 15:38:44 +10:00
parent f8fabd31fa
commit 864d37c3d8
52 changed files with 227 additions and 229 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/nouveau/include/nvkm/core/device.h
View File

@ -60,7 +60,6 @@ struct nvkm_device {
struct notifier_block nb;
} acpi;
struct nvkm_gr *gr;
struct nvkm_engine *ifb;
struct nvkm_engine *me;
struct nvkm_engine *mpeg;
@ -116,7 +115,6 @@ struct nvkm_device_chip {
#undef NVKM_LAYOUT_INST
#undef NVKM_LAYOUT_ONCE
int (*gr )(struct nvkm_device *, int idx, struct nvkm_gr **);
int (*ifb )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*me )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*mpeg )(struct nvkm_device *, int idx, struct nvkm_engine **);

1
drivers/gpu/drm/nouveau/include/nvkm/core/layout.h
View File

@ -31,4 +31,5 @@ NVKM_LAYOUT_ONCE(NVKM_ENGINE_CIPHER , struct nvkm_engine , cipher)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_DISP , struct nvkm_disp , disp)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_DMAOBJ , struct nvkm_dma , dma)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_FIFO , struct nvkm_fifo , fifo)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_GR , struct nvkm_gr , gr)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_VP , struct nvkm_engine , vp)

80
drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
View File

@ -14,44 +14,44 @@ int nvkm_gr_ctxsw_pause(struct nvkm_device *);
int nvkm_gr_ctxsw_resume(struct nvkm_device *);
u32 nvkm_gr_ctxsw_inst(struct nvkm_device *);
int nv04_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int nv10_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int nv15_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int nv17_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int nv20_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int nv25_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int nv2a_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int nv30_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int nv34_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int nv35_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int nv40_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int nv44_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int nv50_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int g84_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gt200_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int mcp79_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gt215_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int mcp89_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gf100_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gf104_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gf108_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gf110_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gf117_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gf119_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gk104_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gk110_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gk110b_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gk208_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gk20a_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gm107_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gm200_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gm20b_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gp100_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gp102_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gp104_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gp107_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gp108_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gp10b_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int gv100_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int tu102_gr_new(struct nvkm_device *, int, struct nvkm_gr **);
int nv04_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int nv10_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int nv15_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int nv17_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int nv20_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int nv25_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int nv2a_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int nv30_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int nv34_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int nv35_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int nv40_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int nv44_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int nv50_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int g84_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int gt200_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int mcp79_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int gt215_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int mcp89_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int gf100_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int gf104_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int gf108_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int gf110_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int gf117_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int gf119_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int gk104_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int gk110_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int gk110b_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int gk208_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int gk20a_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int gm107_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int gm200_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int gm20b_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int gp100_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int gp102_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int gp104_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int gp107_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int gp108_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int gp10b_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int gv100_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
int tu102_gr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_gr **);
#endif

1
drivers/gpu/drm/nouveau/nvkm/core/subdev.c
View File

@ -33,7 +33,6 @@ nvkm_subdev_type[NVKM_SUBDEV_NR] = {
#include <core/layout.h>
#undef NVKM_LAYOUT_ONCE
#undef NVKM_LAYOUT_INST
[NVKM_ENGINE_GR ] = "gr",
[NVKM_ENGINE_IFB ] = "ifb",
[NVKM_ENGINE_ME ] = "me",
[NVKM_ENGINE_MPEG ] = "mpeg",

169
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View File

@ -91,7 +91,7 @@ nv4_chipset = {
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv04_fifo_new },
.gr = nv04_gr_new,
.gr = { 0x00000001, nv04_gr_new },
.sw = nv04_sw_new,
};
@ -112,7 +112,7 @@ nv5_chipset = {
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv04_fifo_new },
.gr = nv04_gr_new,
.gr = { 0x00000001, nv04_gr_new },
.sw = nv04_sw_new,
};
@ -133,7 +133,7 @@ nv10_chipset = {
.timer = { 0x00000001, nv04_timer_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.gr = nv10_gr_new,
.gr = { 0x00000001, nv10_gr_new },
};
static const struct nvkm_device_chip
@ -154,7 +154,7 @@ nv11_chipset = {
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv10_fifo_new },
.gr = nv15_gr_new,
.gr = { 0x00000001, nv15_gr_new },
.sw = nv10_sw_new,
};
@ -176,7 +176,7 @@ nv15_chipset = {
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv10_fifo_new },
.gr = nv15_gr_new,
.gr = { 0x00000001, nv15_gr_new },
.sw = nv10_sw_new,
};
@ -198,7 +198,7 @@ nv17_chipset = {
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv17_fifo_new },
.gr = nv17_gr_new,
.gr = { 0x00000001, nv17_gr_new },
.sw = nv10_sw_new,
};
@ -220,7 +220,7 @@ nv18_chipset = {
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv17_fifo_new },
.gr = nv17_gr_new,
.gr = { 0x00000001, nv17_gr_new },
.sw = nv10_sw_new,
};
@ -242,7 +242,7 @@ nv1a_chipset = {
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv10_fifo_new },
.gr = nv15_gr_new,
.gr = { 0x00000001, nv15_gr_new },
.sw = nv10_sw_new,
};
@ -264,7 +264,7 @@ nv1f_chipset = {
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv17_fifo_new },
.gr = nv17_gr_new,
.gr = { 0x00000001, nv17_gr_new },
.sw = nv10_sw_new,
};
@ -286,7 +286,7 @@ nv20_chipset = {
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv17_fifo_new },
.gr = nv20_gr_new,
.gr = { 0x00000001, nv20_gr_new },
.sw = nv10_sw_new,
};
@ -308,7 +308,7 @@ nv25_chipset = {
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv17_fifo_new },
.gr = nv25_gr_new,
.gr = { 0x00000001, nv25_gr_new },
.sw = nv10_sw_new,
};
@ -330,7 +330,7 @@ nv28_chipset = {
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv17_fifo_new },
.gr = nv25_gr_new,
.gr = { 0x00000001, nv25_gr_new },
.sw = nv10_sw_new,
};
@ -352,7 +352,7 @@ nv2a_chipset = {
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv17_fifo_new },
.gr = nv2a_gr_new,
.gr = { 0x00000001, nv2a_gr_new },
.sw = nv10_sw_new,
};
@ -374,7 +374,7 @@ nv30_chipset = {
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv17_fifo_new },
.gr = nv30_gr_new,
.gr = { 0x00000001, nv30_gr_new },
.sw = nv10_sw_new,
};
@ -396,7 +396,7 @@ nv31_chipset = {
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv17_fifo_new },
.gr = nv30_gr_new,
.gr = { 0x00000001, nv30_gr_new },
.mpeg = nv31_mpeg_new,
.sw = nv10_sw_new,
};
@ -419,7 +419,7 @@ nv34_chipset = {
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv17_fifo_new },
.gr = nv34_gr_new,
.gr = { 0x00000001, nv34_gr_new },
.mpeg = nv31_mpeg_new,
.sw = nv10_sw_new,
};
@ -442,7 +442,7 @@ nv35_chipset = {
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv17_fifo_new },
.gr = nv35_gr_new,
.gr = { 0x00000001, nv35_gr_new },
.sw = nv10_sw_new,
};
@ -464,7 +464,7 @@ nv36_chipset = {
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv17_fifo_new },
.gr = nv35_gr_new,
.gr = { 0x00000001, nv35_gr_new },
.mpeg = nv31_mpeg_new,
.sw = nv10_sw_new,
};
@ -489,7 +489,7 @@ nv40_chipset = {
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv40_fifo_new },
.gr = nv40_gr_new,
.gr = { 0x00000001, nv40_gr_new },
.mpeg = nv40_mpeg_new,
.pm = nv40_pm_new,
.sw = nv10_sw_new,
@ -515,7 +515,7 @@ nv41_chipset = {
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv40_fifo_new },
.gr = nv40_gr_new,
.gr = { 0x00000001, nv40_gr_new },
.mpeg = nv40_mpeg_new,
.pm = nv40_pm_new,
.sw = nv10_sw_new,
@ -541,7 +541,7 @@ nv42_chipset = {
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv40_fifo_new },
.gr = nv40_gr_new,
.gr = { 0x00000001, nv40_gr_new },
.mpeg = nv40_mpeg_new,
.pm = nv40_pm_new,
.sw = nv10_sw_new,
@ -567,7 +567,7 @@ nv43_chipset = {
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv40_fifo_new },
.gr = nv40_gr_new,
.gr = { 0x00000001, nv40_gr_new },
.mpeg = nv40_mpeg_new,
.pm = nv40_pm_new,
.sw = nv10_sw_new,
@ -593,7 +593,7 @@ nv44_chipset = {
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv40_fifo_new },
.gr = nv44_gr_new,
.gr = { 0x00000001, nv44_gr_new },
.mpeg = nv44_mpeg_new,
.pm = nv40_pm_new,
.sw = nv10_sw_new,
@ -619,7 +619,7 @@ nv45_chipset = {
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv40_fifo_new },
.gr = nv40_gr_new,
.gr = { 0x00000001, nv40_gr_new },
.mpeg = nv44_mpeg_new,
.pm = nv40_pm_new,
.sw = nv10_sw_new,
@ -645,7 +645,7 @@ nv46_chipset = {
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv40_fifo_new },
.gr = nv44_gr_new,
.gr = { 0x00000001, nv44_gr_new },
.mpeg = nv44_mpeg_new,
.pm = nv40_pm_new,
.sw = nv10_sw_new,
@ -671,7 +671,7 @@ nv47_chipset = {
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv40_fifo_new },
.gr = nv40_gr_new,
.gr = { 0x00000001, nv40_gr_new },
.mpeg = nv44_mpeg_new,
.pm = nv40_pm_new,
.sw = nv10_sw_new,
@ -697,7 +697,7 @@ nv49_chipset = {
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv40_fifo_new },
.gr = nv40_gr_new,
.gr = { 0x00000001, nv40_gr_new },
.mpeg = nv44_mpeg_new,
.pm = nv40_pm_new,
.sw = nv10_sw_new,
@ -723,7 +723,7 @@ nv4a_chipset = {
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv40_fifo_new },
.gr = nv44_gr_new,
.gr = { 0x00000001, nv44_gr_new },
.mpeg = nv44_mpeg_new,
.pm = nv40_pm_new,
.sw = nv10_sw_new,
@ -749,7 +749,7 @@ nv4b_chipset = {
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv40_fifo_new },
.gr = nv40_gr_new,
.gr = { 0x00000001, nv40_gr_new },
.mpeg = nv44_mpeg_new,
.pm = nv40_pm_new,
.sw = nv10_sw_new,
@ -775,7 +775,7 @@ nv4c_chipset = {
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv40_fifo_new },
.gr = nv44_gr_new,
.gr = { 0x00000001, nv44_gr_new },
.mpeg = nv44_mpeg_new,
.pm = nv40_pm_new,
.sw = nv10_sw_new,
@ -801,7 +801,7 @@ nv4e_chipset = {
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv40_fifo_new },
.gr = nv44_gr_new,
.gr = { 0x00000001, nv44_gr_new },
.mpeg = nv44_mpeg_new,
.pm = nv40_pm_new,
.sw = nv10_sw_new,
@ -830,7 +830,7 @@ nv50_chipset = {
.disp = { 0x00000001, nv50_disp_new },
.dma = { 0x00000001, nv50_dma_new },
.fifo = { 0x00000001, nv50_fifo_new },
.gr = nv50_gr_new,
.gr = { 0x00000001, nv50_gr_new },
.mpeg = nv50_mpeg_new,
.pm = nv50_pm_new,
.sw = nv50_sw_new,
@ -856,7 +856,7 @@ nv63_chipset = {
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv40_fifo_new },
.gr = nv44_gr_new,
.gr = { 0x00000001, nv44_gr_new },
.mpeg = nv44_mpeg_new,
.pm = nv40_pm_new,
.sw = nv10_sw_new,
@ -882,7 +882,7 @@ nv67_chipset = {
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv40_fifo_new },
.gr = nv44_gr_new,
.gr = { 0x00000001, nv44_gr_new },
.mpeg = nv44_mpeg_new,
.pm = nv40_pm_new,
.sw = nv10_sw_new,
@ -908,7 +908,7 @@ nv68_chipset = {
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = { 0x00000001, nv40_fifo_new },
.gr = nv44_gr_new,
.gr = { 0x00000001, nv44_gr_new },
.mpeg = nv44_mpeg_new,
.pm = nv40_pm_new,
.sw = nv10_sw_new,
@ -939,7 +939,7 @@ nv84_chipset = {
.disp = { 0x00000001, g84_disp_new },
.dma = { 0x00000001, nv50_dma_new },
.fifo = { 0x00000001, g84_fifo_new },
.gr = g84_gr_new,
.gr = { 0x00000001, g84_gr_new },
.mpeg = g84_mpeg_new,
.pm = g84_pm_new,
.sw = nv50_sw_new,
@ -971,7 +971,7 @@ nv86_chipset = {
.disp = { 0x00000001, g84_disp_new },
.dma = { 0x00000001, nv50_dma_new },
.fifo = { 0x00000001, g84_fifo_new },
.gr = g84_gr_new,
.gr = { 0x00000001, g84_gr_new },
.mpeg = g84_mpeg_new,
.pm = g84_pm_new,
.sw = nv50_sw_new,
@ -1003,7 +1003,7 @@ nv92_chipset = {
.disp = { 0x00000001, g84_disp_new },
.dma = { 0x00000001, nv50_dma_new },
.fifo = { 0x00000001, g84_fifo_new },
.gr = g84_gr_new,
.gr = { 0x00000001, g84_gr_new },
.mpeg = g84_mpeg_new,
.pm = g84_pm_new,
.sw = nv50_sw_new,
@ -1035,7 +1035,7 @@ nv94_chipset = {
.disp = { 0x00000001, g94_disp_new },
.dma = { 0x00000001, nv50_dma_new },
.fifo = { 0x00000001, g84_fifo_new },
.gr = g84_gr_new,
.gr = { 0x00000001, g84_gr_new },
.mpeg = g84_mpeg_new,
.pm = g84_pm_new,
.sw = nv50_sw_new,
@ -1067,7 +1067,7 @@ nv96_chipset = {
.disp = { 0x00000001, g94_disp_new },
.dma = { 0x00000001, nv50_dma_new },
.fifo = { 0x00000001, g84_fifo_new },
.gr = g84_gr_new,
.gr = { 0x00000001, g84_gr_new },
.mpeg = g84_mpeg_new,
.pm = g84_pm_new,
.sw = nv50_sw_new,
@ -1097,7 +1097,7 @@ nv98_chipset = {
.disp = { 0x00000001, g94_disp_new },
.dma = { 0x00000001, nv50_dma_new },
.fifo = { 0x00000001, g84_fifo_new },
.gr = g84_gr_new,
.gr = { 0x00000001, g84_gr_new },
.mspdec = g98_mspdec_new,
.msppp = g98_msppp_new,
.msvld = g98_msvld_new,
@ -1131,7 +1131,7 @@ nva0_chipset = {
.disp = { 0x00000001, gt200_disp_new },
.dma = { 0x00000001, nv50_dma_new },
.fifo = { 0x00000001, g84_fifo_new },
.gr = gt200_gr_new,
.gr = { 0x00000001, gt200_gr_new },
.mpeg = g84_mpeg_new,
.pm = gt200_pm_new,
.sw = nv50_sw_new,
@ -1163,7 +1163,7 @@ nva3_chipset = {
.disp = { 0x00000001, gt215_disp_new },
.dma = { 0x00000001, nv50_dma_new },
.fifo = { 0x00000001, g84_fifo_new },
.gr = gt215_gr_new,
.gr = { 0x00000001, gt215_gr_new },
.mpeg = g84_mpeg_new,
.mspdec = gt215_mspdec_new,
.msppp = gt215_msppp_new,
@ -1197,7 +1197,7 @@ nva5_chipset = {
.disp = { 0x00000001, gt215_disp_new },
.dma = { 0x00000001, nv50_dma_new },
.fifo = { 0x00000001, g84_fifo_new },
.gr = gt215_gr_new,
.gr = { 0x00000001, gt215_gr_new },
.mspdec = gt215_mspdec_new,
.msppp = gt215_msppp_new,
.msvld = gt215_msvld_new,
@ -1230,7 +1230,7 @@ nva8_chipset = {
.disp = { 0x00000001, gt215_disp_new },
.dma = { 0x00000001, nv50_dma_new },
.fifo = { 0x00000001, g84_fifo_new },
.gr = gt215_gr_new,
.gr = { 0x00000001, gt215_gr_new },
.mspdec = gt215_mspdec_new,
.msppp = gt215_msppp_new,
.msvld = gt215_msvld_new,
@ -1261,7 +1261,7 @@ nvaa_chipset = {
.disp = { 0x00000001, mcp77_disp_new },
.dma = { 0x00000001, nv50_dma_new },
.fifo = { 0x00000001, g84_fifo_new },
.gr = gt200_gr_new,
.gr = { 0x00000001, gt200_gr_new },
.mspdec = g98_mspdec_new,
.msppp = g98_msppp_new,
.msvld = g98_msvld_new,
@ -1293,7 +1293,7 @@ nvac_chipset = {
.disp = { 0x00000001, mcp77_disp_new },
.dma = { 0x00000001, nv50_dma_new },
.fifo = { 0x00000001, g84_fifo_new },
.gr = mcp79_gr_new,
.gr = { 0x00000001, mcp79_gr_new },
.mspdec = g98_mspdec_new,
.msppp = g98_msppp_new,
.msvld = g98_msvld_new,
@ -1327,7 +1327,7 @@ nvaf_chipset = {
.disp = { 0x00000001, mcp89_disp_new },
.dma = { 0x00000001, nv50_dma_new },
.fifo = { 0x00000001, g84_fifo_new },
.gr = mcp89_gr_new,
.gr = { 0x00000001, mcp89_gr_new },
.mspdec = gt215_mspdec_new,
.msppp = gt215_msppp_new,
.msvld = mcp89_msvld_new,
@ -1363,7 +1363,7 @@ nvc0_chipset = {
.disp = { 0x00000001, gt215_disp_new },
.dma = { 0x00000001, gf100_dma_new },
.fifo = { 0x00000001, gf100_fifo_new },
.gr = gf100_gr_new,
.gr = { 0x00000001, gf100_gr_new },
.mspdec = gf100_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gf100_msvld_new,
@ -1399,7 +1399,7 @@ nvc1_chipset = {
.disp = { 0x00000001, gt215_disp_new },
.dma = { 0x00000001, gf100_dma_new },
.fifo = { 0x00000001, gf100_fifo_new },
.gr = gf108_gr_new,
.gr = { 0x00000001, gf108_gr_new },
.mspdec = gf100_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gf100_msvld_new,
@ -1435,7 +1435,7 @@ nvc3_chipset = {
.disp = { 0x00000001, gt215_disp_new },
.dma = { 0x00000001, gf100_dma_new },
.fifo = { 0x00000001, gf100_fifo_new },
.gr = gf104_gr_new,
.gr = { 0x00000001, gf104_gr_new },
.mspdec = gf100_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gf100_msvld_new,
@ -1471,7 +1471,7 @@ nvc4_chipset = {
.disp = { 0x00000001, gt215_disp_new },
.dma = { 0x00000001, gf100_dma_new },
.fifo = { 0x00000001, gf100_fifo_new },
.gr = gf104_gr_new,
.gr = { 0x00000001, gf104_gr_new },
.mspdec = gf100_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gf100_msvld_new,
@ -1507,7 +1507,7 @@ nvc8_chipset = {
.disp = { 0x00000001, gt215_disp_new },
.dma = { 0x00000001, gf100_dma_new },
.fifo = { 0x00000001, gf100_fifo_new },
.gr = gf110_gr_new,
.gr = { 0x00000001, gf110_gr_new },
.mspdec = gf100_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gf100_msvld_new,
@ -1543,7 +1543,7 @@ nvce_chipset = {
.disp = { 0x00000001, gt215_disp_new },
.dma = { 0x00000001, gf100_dma_new },
.fifo = { 0x00000001, gf100_fifo_new },
.gr = gf104_gr_new,
.gr = { 0x00000001, gf104_gr_new },
.mspdec = gf100_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gf100_msvld_new,
@ -1579,7 +1579,7 @@ nvcf_chipset = {
.disp = { 0x00000001, gt215_disp_new },
.dma = { 0x00000001, gf100_dma_new },
.fifo = { 0x00000001, gf100_fifo_new },
.gr = gf104_gr_new,
.gr = { 0x00000001, gf104_gr_new },
.mspdec = gf100_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gf100_msvld_new,
@ -1614,7 +1614,7 @@ nvd7_chipset = {
.disp = { 0x00000001, gf119_disp_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gf100_fifo_new },
.gr = gf117_gr_new,
.gr = { 0x00000001, gf117_gr_new },
.mspdec = gf100_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gf100_msvld_new,
@ -1650,7 +1650,7 @@ nvd9_chipset = {
.disp = { 0x00000001, gf119_disp_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gf100_fifo_new },
.gr = gf119_gr_new,
.gr = { 0x00000001, gf119_gr_new },
.mspdec = gf100_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gf100_msvld_new,
@ -1687,7 +1687,7 @@ nve4_chipset = {
.disp = { 0x00000001, gk104_disp_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gk104_fifo_new },
.gr = gk104_gr_new,
.gr = { 0x00000001, gk104_gr_new },
.mspdec = gk104_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gk104_msvld_new,
@ -1724,7 +1724,7 @@ nve6_chipset = {
.disp = { 0x00000001, gk104_disp_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gk104_fifo_new },
.gr = gk104_gr_new,
.gr = { 0x00000001, gk104_gr_new },
.mspdec = gk104_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gk104_msvld_new,
@ -1761,7 +1761,7 @@ nve7_chipset = {
.disp = { 0x00000001, gk104_disp_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gk104_fifo_new },
.gr = gk104_gr_new,
.gr = { 0x00000001, gk104_gr_new },
.mspdec = gk104_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gk104_msvld_new,
@ -1789,7 +1789,7 @@ nvea_chipset = {
.ce = { 0x00000004, gk104_ce_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gk20a_fifo_new },
.gr = gk20a_gr_new,
.gr = { 0x00000001, gk20a_gr_new },
.pm = gk104_pm_new,
.sw = gf100_sw_new,
};
@ -1823,7 +1823,7 @@ nvf0_chipset = {
.disp = { 0x00000001, gk110_disp_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gk110_fifo_new },
.gr = gk110_gr_new,
.gr = { 0x00000001, gk110_gr_new },
.mspdec = gk104_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gk104_msvld_new,
@ -1859,7 +1859,7 @@ nvf1_chipset = {
.disp = { 0x00000001, gk110_disp_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gk110_fifo_new },
.gr = gk110b_gr_new,
.gr = { 0x00000001, gk110b_gr_new },
.mspdec = gk104_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gk104_msvld_new,
@ -1895,7 +1895,7 @@ nv106_chipset = {
.disp = { 0x00000001, gk110_disp_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gk208_fifo_new },
.gr = gk208_gr_new,
.gr = { 0x00000001, gk208_gr_new },
.mspdec = gk104_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gk104_msvld_new,
@ -1931,7 +1931,7 @@ nv108_chipset = {
.disp = { 0x00000001, gk110_disp_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gk208_fifo_new },
.gr = gk208_gr_new,
.gr = { 0x00000001, gk208_gr_new },
.mspdec = gk104_mspdec_new,
.msppp = gf100_msppp_new,
.msvld = gk104_msvld_new,
@ -1967,7 +1967,7 @@ nv117_chipset = {
.disp = { 0x00000001, gm107_disp_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gm107_fifo_new },
.gr = gm107_gr_new,
.gr = { 0x00000001, gm107_gr_new },
.nvdec[0] = gm107_nvdec_new,
.nvenc[0] = gm107_nvenc_new,
.sw = gf100_sw_new,
@ -2002,7 +2002,7 @@ nv118_chipset = {
.disp = { 0x00000001, gm107_disp_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gm107_fifo_new },
.gr = gm107_gr_new,
.gr = { 0x00000001, gm107_gr_new },
.sw = gf100_sw_new,
};
@ -2035,7 +2035,7 @@ nv120_chipset = {
.disp = { 0x00000001, gm200_disp_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gm200_fifo_new },
.gr = gm200_gr_new,
.gr = { 0x00000001, gm200_gr_new },
.nvdec[0] = gm107_nvdec_new,
.nvenc[0] = gm107_nvenc_new,
.nvenc[1] = gm107_nvenc_new,
@ -2071,7 +2071,7 @@ nv124_chipset = {
.disp = { 0x00000001, gm200_disp_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gm200_fifo_new },
.gr = gm200_gr_new,
.gr = { 0x00000001, gm200_gr_new },
.nvdec[0] = gm107_nvdec_new,
.nvenc[0] = gm107_nvenc_new,
.nvenc[1] = gm107_nvenc_new,
@ -2107,7 +2107,7 @@ nv126_chipset = {
.disp = { 0x00000001, gm200_disp_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gm200_fifo_new },
.gr = gm200_gr_new,
.gr = { 0x00000001, gm200_gr_new },
.nvdec[0] = gm107_nvdec_new,
.nvenc[0] = gm107_nvenc_new,
.sw = gf100_sw_new,
@ -2134,7 +2134,7 @@ nv12b_chipset = {
.ce = { 0x00000004, gm200_ce_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gm20b_fifo_new },
.gr = gm20b_gr_new,
.gr = { 0x00000001, gm20b_gr_new },
.sw = gf100_sw_new,
};
@ -2165,7 +2165,7 @@ nv130_chipset = {
.dma = { 0x00000001, gf119_dma_new },
.disp = { 0x00000001, gp100_disp_new },
.fifo = { 0x00000001, gp100_fifo_new },
.gr = gp100_gr_new,
.gr = { 0x00000001, gp100_gr_new },
.nvdec[0] = gm107_nvdec_new,
.nvenc[0] = gm107_nvenc_new,
.nvenc[1] = gm107_nvenc_new,
@ -2200,7 +2200,7 @@ nv132_chipset = {
.disp = { 0x00000001, gp102_disp_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gp100_fifo_new },
.gr = gp102_gr_new,
.gr = { 0x00000001, gp102_gr_new },
.nvdec[0] = gm107_nvdec_new,
.nvenc[0] = gm107_nvenc_new,
.nvenc[1] = gm107_nvenc_new,
@ -2235,7 +2235,7 @@ nv134_chipset = {
.disp = { 0x00000001, gp102_disp_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gp100_fifo_new },
.gr = gp104_gr_new,
.gr = { 0x00000001, gp104_gr_new },
.nvdec[0] = gm107_nvdec_new,
.nvenc[0] = gm107_nvenc_new,
.nvenc[1] = gm107_nvenc_new,
@ -2270,7 +2270,7 @@ nv136_chipset = {
.disp = { 0x00000001, gp102_disp_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gp100_fifo_new },
.gr = gp104_gr_new,
.gr = { 0x00000001, gp104_gr_new },
.nvdec[0] = gm107_nvdec_new,
.nvenc[0] = gm107_nvenc_new,
.sec2 = gp102_sec2_new,
@ -2304,7 +2304,7 @@ nv137_chipset = {
.disp = { 0x00000001, gp102_disp_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gp100_fifo_new },
.gr = gp107_gr_new,
.gr = { 0x00000001, gp107_gr_new },
.nvdec[0] = gm107_nvdec_new,
.nvenc[0] = gm107_nvenc_new,
.nvenc[1] = gm107_nvenc_new,
@ -2339,7 +2339,7 @@ nv138_chipset = {
.disp = { 0x00000001, gp102_disp_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gp100_fifo_new },
.gr = gp108_gr_new,
.gr = { 0x00000001, gp108_gr_new },
.nvdec[0] = gm107_nvdec_new,
.sec2 = gp108_sec2_new,
.sw = gf100_sw_new,
@ -2365,7 +2365,7 @@ nv13b_chipset = {
.ce = { 0x00000001, gp100_ce_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gp10b_fifo_new },
.gr = gp10b_gr_new,
.gr = { 0x00000001, gp10b_gr_new },
.sw = gf100_sw_new,
};
@ -2397,7 +2397,7 @@ nv140_chipset = {
.disp = { 0x00000001, gv100_disp_new },
.dma = { 0x00000001, gv100_dma_new },
.fifo = { 0x00000001, gv100_fifo_new },
.gr = gv100_gr_new,
.gr = { 0x00000001, gv100_gr_new },
.nvdec[0] = gm107_nvdec_new,
.nvenc[0] = gm107_nvenc_new,
.nvenc[1] = gm107_nvenc_new,
@ -2433,7 +2433,7 @@ nv162_chipset = {
.disp = { 0x00000001, tu102_disp_new },
.dma = { 0x00000001, gv100_dma_new },
.fifo = { 0x00000001, tu102_fifo_new },
.gr = tu102_gr_new,
.gr = { 0x00000001, tu102_gr_new },
.nvdec[0] = gm107_nvdec_new,
.nvenc[0] = gm107_nvenc_new,
.sec2 = tu102_sec2_new,
@ -2467,7 +2467,7 @@ nv164_chipset = {
.disp = { 0x00000001, tu102_disp_new },
.dma = { 0x00000001, gv100_dma_new },
.fifo = { 0x00000001, tu102_fifo_new },
.gr = tu102_gr_new,
.gr = { 0x00000001, tu102_gr_new },
.nvdec[0] = gm107_nvdec_new,
.nvdec[1] = gm107_nvdec_new,
.nvenc[0] = gm107_nvenc_new,
@ -2502,7 +2502,7 @@ nv166_chipset = {
.disp = { 0x00000001, tu102_disp_new },
.dma = { 0x00000001, gv100_dma_new },
.fifo = { 0x00000001, tu102_fifo_new },
.gr = tu102_gr_new,
.gr = { 0x00000001, tu102_gr_new },
.nvdec[0] = gm107_nvdec_new,
.nvdec[1] = gm107_nvdec_new,
.nvdec[2] = gm107_nvdec_new,
@ -2538,7 +2538,7 @@ nv167_chipset = {
.disp = { 0x00000001, tu102_disp_new },
.dma = { 0x00000001, gv100_dma_new },
.fifo = { 0x00000001, tu102_fifo_new },
.gr = tu102_gr_new,
.gr = { 0x00000001, tu102_gr_new },
.nvdec[0] = gm107_nvdec_new,
.nvenc[0] = gm107_nvenc_new,
.sec2 = tu102_sec2_new,
@ -2572,7 +2572,7 @@ nv168_chipset = {
.disp = { 0x00000001, tu102_disp_new },
.dma = { 0x00000001, gv100_dma_new },
.fifo = { 0x00000001, tu102_fifo_new },
.gr = tu102_gr_new,
.gr = { 0x00000001, tu102_gr_new },
.nvdec[0] = gm107_nvdec_new,
.nvenc[0] = gm107_nvenc_new,
.sec2 = tu102_sec2_new,
@ -3174,7 +3174,6 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
#include <core/layout.h>
#undef NVKM_LAYOUT_INST
#undef NVKM_LAYOUT_ONCE
_(NVKM_ENGINE_GR , gr);
_(NVKM_ENGINE_IFB , ifb);
_(NVKM_ENGINE_ME , me);
_(NVKM_ENGINE_MPEG , mpeg);

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c
View File

@ -175,8 +175,8 @@ nvkm_gr = {
int
nvkm_gr_ctor(const struct nvkm_gr_func *func, struct nvkm_device *device,
int index, bool enable, struct nvkm_gr *gr)
enum nvkm_subdev_type type, int inst, bool enable, struct nvkm_gr *gr)
{
gr->func = func;
return nvkm_engine_ctor(&nvkm_gr, device, index, enable, &gr->engine);
return nvkm_engine_ctor(&nvkm_gr, device, type, inst, enable, &gr->engine);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c
View File

@ -192,7 +192,7 @@ g84_gr = {
};
int
g84_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
g84_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return nv50_gr_new_(&g84_gr, device, index, pgr);
return nv50_gr_new_(&g84_gr, device, type, inst, pgr);
}

10
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
View File

@ -2087,8 +2087,8 @@ gf100_gr_flcn = {
};
int
gf100_gr_new_(const struct gf100_gr_fwif *fwif,
struct nvkm_device *device, int index, struct nvkm_gr **pgr)
gf100_gr_new_(const struct gf100_gr_fwif *fwif, struct nvkm_device *device,
enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
struct gf100_gr *gr;
int ret;
@ -2097,7 +2097,7 @@ gf100_gr_new_(const struct gf100_gr_fwif *fwif,
return -ENOMEM;
*pgr = &gr->base;
ret = nvkm_gr_ctor(&gf100_gr_, device, index, true, &gr->base);
ret = nvkm_gr_ctor(&gf100_gr_, device, type, inst, true, &gr->base);
if (ret)
return ret;
@ -2483,7 +2483,7 @@ gf100_gr_fwif[] = {
};
int
gf100_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
gf100_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(gf100_gr_fwif, device, index, pgr);
return gf100_gr_new_(gf100_gr_fwif, device, type, inst, pgr);
}

2
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
View File

@ -416,6 +416,6 @@ void gm20b_gr_acr_bld_patch(struct nvkm_acr *, u32, s64);
extern const struct nvkm_acr_lsf_func gp108_gr_gpccs_acr;
extern const struct nvkm_acr_lsf_func gp108_gr_fecs_acr;
int gf100_gr_new_(const struct gf100_gr_fwif *, struct nvkm_device *, int,
int gf100_gr_new_(const struct gf100_gr_fwif *, struct nvkm_device *, enum nvkm_subdev_type, int,
struct nvkm_gr **);
#endif

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c
View File

@ -152,7 +152,7 @@ gf104_gr_fwif[] = {
};
int
gf104_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
gf104_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(gf104_gr_fwif, device, index, pgr);
return gf100_gr_new_(gf104_gr_fwif, device, type, inst, pgr);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c
View File

@ -151,7 +151,7 @@ gf108_gr_fwif[] = {
};
int
gf108_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
gf108_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(gf108_gr_fwif, device, index, pgr);
return gf100_gr_new_(gf108_gr_fwif, device, type, inst, pgr);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c
View File

@ -127,7 +127,7 @@ gf110_gr_fwif[] = {
};
int
gf110_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
gf110_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(gf110_gr_fwif, device, index, pgr);
return gf100_gr_new_(gf110_gr_fwif, device, type, inst, pgr);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c
View File

@ -192,7 +192,7 @@ gf117_gr_fwif[] = {
};
int
gf117_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
gf117_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(gf117_gr_fwif, device, index, pgr);
return gf100_gr_new_(gf117_gr_fwif, device, type, inst, pgr);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c
View File

@ -218,7 +218,7 @@ gf119_gr_fwif[] = {
};
int
gf119_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
gf119_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(gf119_gr_fwif, device, index, pgr);
return gf100_gr_new_(gf119_gr_fwif, device, type, inst, pgr);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c
View File

@ -497,7 +497,7 @@ gk104_gr_fwif[] = {
};
int
gk104_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
gk104_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(gk104_gr_fwif, device, index, pgr);
return gf100_gr_new_(gk104_gr_fwif, device, type, inst, pgr);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c
View File

@ -393,7 +393,7 @@ gk110_gr_fwif[] = {
};
int
gk110_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
gk110_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(gk110_gr_fwif, device, index, pgr);
return gf100_gr_new_(gk110_gr_fwif, device, type, inst, pgr);
}

5
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c
View File

@ -144,7 +144,8 @@ gk110b_gr_fwif[] = {
};
int
gk110b_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
gk110b_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_gr **pgr)
{
return gf100_gr_new_(gk110b_gr_fwif, device, index, pgr);
return gf100_gr_new_(gk110b_gr_fwif, device, type, inst, pgr);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c
View File

@ -202,7 +202,7 @@ gk208_gr_fwif[] = {
};
int
gk208_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
gk208_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(gk208_gr_fwif, device, index, pgr);
return gf100_gr_new_(gk208_gr_fwif, device, type, inst, pgr);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c
View File

@ -357,7 +357,7 @@ gk20a_gr_fwif[] = {
};
int
gk20a_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
gk20a_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(gk20a_gr_fwif, device, index, pgr);
return gf100_gr_new_(gk20a_gr_fwif, device, type, inst, pgr);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c
View File

@ -437,7 +437,7 @@ gm107_gr_fwif[] = {
};
int
gm107_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
gm107_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(gm107_gr_fwif, device, index, pgr);
return gf100_gr_new_(gm107_gr_fwif, device, type, inst, pgr);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c
View File

@ -288,7 +288,7 @@ gm200_gr_fwif[] = {
};
int
gm200_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
gm200_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(gm200_gr_fwif, device, index, pgr);
return gf100_gr_new_(gm200_gr_fwif, device, type, inst, pgr);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c
View File

@ -181,7 +181,7 @@ gm20b_gr_fwif[] = {
};
int
gm20b_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
gm20b_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(gm20b_gr_fwif, device, index, pgr);
return gf100_gr_new_(gm20b_gr_fwif, device, type, inst, pgr);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c
View File

@ -156,7 +156,7 @@ gp100_gr_fwif[] = {
};
int
gp100_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
gp100_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(gp100_gr_fwif, device, index, pgr);
return gf100_gr_new_(gp100_gr_fwif, device, type, inst, pgr);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c
View File

@ -152,7 +152,7 @@ gp102_gr_fwif[] = {
};
int
gp102_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
gp102_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(gp102_gr_fwif, device, index, pgr);
return gf100_gr_new_(gp102_gr_fwif, device, type, inst, pgr);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp104.c
View File

@ -93,7 +93,7 @@ gp104_gr_fwif[] = {
};
int
gp104_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
gp104_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(gp104_gr_fwif, device, index, pgr);
return gf100_gr_new_(gp104_gr_fwif, device, type, inst, pgr);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp107.c
View File

@ -82,7 +82,7 @@ gp107_gr_fwif[] = {
};
int
gp107_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
gp107_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(gp107_gr_fwif, device, index, pgr);
return gf100_gr_new_(gp107_gr_fwif, device, type, inst, pgr);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp108.c
View File

@ -92,7 +92,7 @@ gp108_gr_fwif[] = {
};
int
gp108_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
gp108_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(gp108_gr_fwif, device, index, pgr);
return gf100_gr_new_(gp108_gr_fwif, device, type, inst, pgr);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp10b.c
View File

@ -94,7 +94,7 @@ gp10b_gr_fwif[] = {
};
int
gp10b_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
gp10b_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(gp10b_gr_fwif, device, index, pgr);
return gf100_gr_new_(gp10b_gr_fwif, device, type, inst, pgr);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/gt200.c
View File

@ -43,7 +43,7 @@ gt200_gr = {
};
int
gt200_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
gt200_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return nv50_gr_new_(&gt200_gr, device, index, pgr);
return nv50_gr_new_(&gt200_gr, device, type, inst, pgr);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/gt215.c
View File

@ -44,7 +44,7 @@ gt215_gr = {
};
int
gt215_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
gt215_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return nv50_gr_new_(&gt215_gr, device, index, pgr);
return nv50_gr_new_(&gt215_gr, device, type, inst, pgr);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c
View File

@ -141,7 +141,7 @@ gv100_gr_fwif[] = {
};
int
gv100_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
gv100_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(gv100_gr_fwif, device, index, pgr);
return gf100_gr_new_(gv100_gr_fwif, device, type, inst, pgr);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp79.c
View File

@ -42,7 +42,7 @@ mcp79_gr = {
};
int
mcp79_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
mcp79_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return nv50_gr_new_(&mcp79_gr, device, index, pgr);
return nv50_gr_new_(&mcp79_gr, device, type, inst, pgr);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp89.c
View File

@ -44,7 +44,7 @@ mcp89_gr = {
};
int
mcp89_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
mcp89_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return nv50_gr_new_(&mcp89_gr, device, index, pgr);
return nv50_gr_new_(&mcp89_gr, device, type, inst, pgr);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
View File

@ -1413,7 +1413,7 @@ nv04_gr = {
};
int
nv04_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
nv04_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
struct nv04_gr *gr;
@ -1422,5 +1422,5 @@ nv04_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
spin_lock_init(&gr->lock);
*pgr = &gr->base;
return nvkm_gr_ctor(&nv04_gr, device, index, true, &gr->base);
return nvkm_gr_ctor(&nv04_gr, device, type, inst, true, &gr->base);
}

8
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c
View File

@ -1173,7 +1173,7 @@ nv10_gr_init(struct nvkm_gr *base)
int
nv10_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device,
int index, struct nvkm_gr **pgr)
enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
struct nv10_gr *gr;
@ -1182,7 +1182,7 @@ nv10_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device,
spin_lock_init(&gr->lock);
*pgr = &gr->base;
return nvkm_gr_ctor(func, device, index, true, &gr->base);
return nvkm_gr_ctor(func, device, type, inst, true, &gr->base);
}
static const struct nvkm_gr_func
@ -1215,7 +1215,7 @@ nv10_gr = {
};
int
nv10_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
nv10_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return nv10_gr_new_(&nv10_gr, device, index, pgr);
return nv10_gr_new_(&nv10_gr, device, type, inst, pgr);
}

2
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.h
View File

@ -3,7 +3,7 @@
#define __NV10_GR_H__
#include "priv.h"
int nv10_gr_new_(const struct nvkm_gr_func *, struct nvkm_device *, int index,
int nv10_gr_new_(const struct nvkm_gr_func *, struct nvkm_device *, enum nvkm_subdev_type, int,
struct nvkm_gr **);
int nv10_gr_init(struct nvkm_gr *);
void nv10_gr_intr(struct nvkm_gr *);

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv15.c
View File

@ -53,7 +53,7 @@ nv15_gr = {
};
int
nv15_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
nv15_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return nv10_gr_new_(&nv15_gr, device, index, pgr);
return nv10_gr_new_(&nv15_gr, device, type, inst, pgr);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv17.c
View File

@ -53,7 +53,7 @@ nv17_gr = {
};
int
nv17_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
nv17_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return nv10_gr_new_(&nv17_gr, device, index, pgr);
return nv10_gr_new_(&nv17_gr, device, type, inst, pgr);
}

8
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
View File

@ -330,7 +330,7 @@ nv20_gr_dtor(struct nvkm_gr *base)
int
nv20_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device,
int index, struct nvkm_gr **pgr)
enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
struct nv20_gr *gr;
@ -338,7 +338,7 @@ nv20_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device,
return -ENOMEM;
*pgr = &gr->base;
return nvkm_gr_ctor(func, device, index, true, &gr->base);
return nvkm_gr_ctor(func, device, type, inst, true, &gr->base);
}
static const struct nvkm_gr_func
@ -370,7 +370,7 @@ nv20_gr = {
};
int
nv20_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
nv20_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return nv20_gr_new_(&nv20_gr, device, index, pgr);
return nv20_gr_new_(&nv20_gr, device, type, inst, pgr);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h
View File

@ -9,8 +9,8 @@ struct nv20_gr {
struct nvkm_memory *ctxtab;
};
int nv20_gr_new_(const struct nvkm_gr_func *, struct nvkm_device *,
int, struct nvkm_gr **);
int nv20_gr_new_(const struct nvkm_gr_func *, struct nvkm_device *, enum nvkm_subdev_type, int,
struct nvkm_gr **);
void *nv20_gr_dtor(struct nvkm_gr *);
int nv20_gr_oneinit(struct nvkm_gr *);
int nv20_gr_init(struct nvkm_gr *);

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
View File

@ -129,7 +129,7 @@ nv25_gr = {
};
int
nv25_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
nv25_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return nv20_gr_new_(&nv25_gr, device, index, pgr);
return nv20_gr_new_(&nv25_gr, device, type, inst, pgr);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
View File

@ -120,7 +120,7 @@ nv2a_gr = {
};
int
nv2a_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
nv2a_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return nv20_gr_new_(&nv2a_gr, device, index, pgr);
return nv20_gr_new_(&nv2a_gr, device, type, inst, pgr);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
View File

@ -194,7 +194,7 @@ nv30_gr = {
};
int
nv30_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
nv30_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return nv20_gr_new_(&nv30_gr, device, index, pgr);
return nv20_gr_new_(&nv30_gr, device, type, inst, pgr);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
View File

@ -131,7 +131,7 @@ nv34_gr = {
};
int
nv34_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
nv34_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return nv20_gr_new_(&nv34_gr, device, index, pgr);
return nv20_gr_new_(&nv34_gr, device, type, inst, pgr);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
View File

@ -131,7 +131,7 @@ nv35_gr = {
};
int
nv35_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
nv35_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return nv20_gr_new_(&nv35_gr, device, index, pgr);
return nv20_gr_new_(&nv35_gr, device, type, inst, pgr);
}

8
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c
View File

@ -429,7 +429,7 @@ nv40_gr_init(struct nvkm_gr *base)
int
nv40_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device,
int index, struct nvkm_gr **pgr)
enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
struct nv40_gr *gr;
@ -438,7 +438,7 @@ nv40_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device,
*pgr = &gr->base;
INIT_LIST_HEAD(&gr->chan);
return nvkm_gr_ctor(func, device, index, true, &gr->base);
return nvkm_gr_ctor(func, device, type, inst, true, &gr->base);
}
static const struct nvkm_gr_func
@ -470,7 +470,7 @@ nv40_gr = {
};
int
nv40_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
nv40_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return nv40_gr_new_(&nv40_gr, device, index, pgr);
return nv40_gr_new_(&nv40_gr, device, type, inst, pgr);
}

2
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h
View File

@ -10,7 +10,7 @@ struct nv40_gr {
struct list_head chan;
};
int nv40_gr_new_(const struct nvkm_gr_func *, struct nvkm_device *, int index,
int nv40_gr_new_(const struct nvkm_gr_func *, struct nvkm_device *, enum nvkm_subdev_type, int,
struct nvkm_gr **);
int nv40_gr_init(struct nvkm_gr *);
void nv40_gr_intr(struct nvkm_gr *);

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c
View File

@ -102,7 +102,7 @@ nv44_gr = {
};
int
nv44_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
nv44_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return nv40_gr_new_(&nv44_gr, device, index, pgr);
return nv40_gr_new_(&nv44_gr, device, type, inst, pgr);
}

8
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
View File

@ -761,7 +761,7 @@ nv50_gr_init(struct nvkm_gr *base)
int
nv50_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device,
int index, struct nvkm_gr **pgr)
enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
struct nv50_gr *gr;
@ -770,7 +770,7 @@ nv50_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device,
spin_lock_init(&gr->lock);
*pgr = &gr->base;
return nvkm_gr_ctor(func, device, index, true, &gr->base);
return nvkm_gr_ctor(func, device, type, inst, true, &gr->base);
}
static const struct nvkm_gr_func
@ -790,7 +790,7 @@ nv50_gr = {
};
int
nv50_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
nv50_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return nv50_gr_new_(&nv50_gr, device, index, pgr);
return nv50_gr_new_(&nv50_gr, device, type, inst, pgr);
}

2
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h
View File

@ -11,7 +11,7 @@ struct nv50_gr {
u32 size;
};
int nv50_gr_new_(const struct nvkm_gr_func *, struct nvkm_device *, int index,
int nv50_gr_new_(const struct nvkm_gr_func *, struct nvkm_device *, enum nvkm_subdev_type, int,
struct nvkm_gr **);
int nv50_gr_init(struct nvkm_gr *);
void nv50_gr_intr(struct nvkm_gr *);

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h
View File

@ -7,8 +7,8 @@
struct nvkm_fb_tile;
struct nvkm_fifo_chan;
int nvkm_gr_ctor(const struct nvkm_gr_func *, struct nvkm_device *,
int index, bool enable, struct nvkm_gr *);
int nvkm_gr_ctor(const struct nvkm_gr_func *, struct nvkm_device *, enum nvkm_subdev_type, int,
bool enable, struct nvkm_gr *);
bool nv04_gr_idle(struct nvkm_gr *);

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/tu102.c
View File

@ -198,7 +198,7 @@ tu102_gr_fwif[] = {
};
int
tu102_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
tu102_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
{
return gf100_gr_new_(tu102_gr_fwif, device, index, pgr);
return gf100_gr_new_(tu102_gr_fwif, device, type, inst, pgr);
}