forked from Minki/linux
i40e: Implementation of ERROR state for NVM update state machine
This patch adds I40E_NVMUPD_STATE_ERROR state for NVM update. Without this patch driver has no possibility to return NVM image write failure.This state is being set when ARQ rises error. arq_last_status is also updated every time when ARQ event comes, not only on error cases. Change-ID: I67ce43ba22a240773c2821b436e96054db0b7c81 Signed-off-by: Maciej Sosin <maciej.sosin@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
parent
999b315d39
commit
81fa7c97be
@ -964,11 +964,11 @@ i40e_status i40e_clean_arq_element(struct i40e_hw *hw,
|
||||
desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc);
|
||||
desc_idx = ntc;
|
||||
|
||||
hw->aq.arq_last_status =
|
||||
(enum i40e_admin_queue_err)le16_to_cpu(desc->retval);
|
||||
flags = le16_to_cpu(desc->flags);
|
||||
if (flags & I40E_AQ_FLAG_ERR) {
|
||||
ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
|
||||
hw->aq.arq_last_status =
|
||||
(enum i40e_admin_queue_err)le16_to_cpu(desc->retval);
|
||||
i40e_debug(hw,
|
||||
I40E_DEBUG_AQ_MESSAGE,
|
||||
"AQRX: Event received with error 0x%X.\n",
|
||||
|
@ -722,9 +722,20 @@ i40e_status i40e_nvmupd_command(struct i40e_hw *hw,
|
||||
*((u16 *)&bytes[2]) = hw->nvm_wait_opcode;
|
||||
}
|
||||
|
||||
/* Clear error status on read */
|
||||
if (hw->nvmupd_state == I40E_NVMUPD_STATE_ERROR)
|
||||
hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Clear status even it is not read and log */
|
||||
if (hw->nvmupd_state == I40E_NVMUPD_STATE_ERROR) {
|
||||
i40e_debug(hw, I40E_DEBUG_NVM,
|
||||
"Clearing I40E_NVMUPD_STATE_ERROR state without reading\n");
|
||||
hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
|
||||
}
|
||||
|
||||
switch (hw->nvmupd_state) {
|
||||
case I40E_NVMUPD_STATE_INIT:
|
||||
status = i40e_nvmupd_state_init(hw, cmd, bytes, perrno);
|
||||
@ -1074,6 +1085,11 @@ void i40e_nvmupd_check_wait_event(struct i40e_hw *hw, u16 opcode)
|
||||
}
|
||||
hw->nvm_wait_opcode = 0;
|
||||
|
||||
if (hw->aq.arq_last_status) {
|
||||
hw->nvmupd_state = I40E_NVMUPD_STATE_ERROR;
|
||||
return;
|
||||
}
|
||||
|
||||
switch (hw->nvmupd_state) {
|
||||
case I40E_NVMUPD_STATE_INIT_WAIT:
|
||||
hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
|
||||
|
@ -366,6 +366,7 @@ enum i40e_nvmupd_state {
|
||||
I40E_NVMUPD_STATE_WRITING,
|
||||
I40E_NVMUPD_STATE_INIT_WAIT,
|
||||
I40E_NVMUPD_STATE_WRITE_WAIT,
|
||||
I40E_NVMUPD_STATE_ERROR
|
||||
};
|
||||
|
||||
/* nvm_access definition and its masks/shifts need to be accessible to
|
||||
|
@ -912,11 +912,11 @@ i40e_status i40evf_clean_arq_element(struct i40e_hw *hw,
|
||||
desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc);
|
||||
desc_idx = ntc;
|
||||
|
||||
hw->aq.arq_last_status =
|
||||
(enum i40e_admin_queue_err)le16_to_cpu(desc->retval);
|
||||
flags = le16_to_cpu(desc->flags);
|
||||
if (flags & I40E_AQ_FLAG_ERR) {
|
||||
ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
|
||||
hw->aq.arq_last_status =
|
||||
(enum i40e_admin_queue_err)le16_to_cpu(desc->retval);
|
||||
i40e_debug(hw,
|
||||
I40E_DEBUG_AQ_MESSAGE,
|
||||
"AQRX: Event received with error 0x%X.\n",
|
||||
|
@ -348,6 +348,7 @@ enum i40e_nvmupd_state {
|
||||
I40E_NVMUPD_STATE_WRITING,
|
||||
I40E_NVMUPD_STATE_INIT_WAIT,
|
||||
I40E_NVMUPD_STATE_WRITE_WAIT,
|
||||
I40E_NVMUPD_STATE_ERROR
|
||||
};
|
||||
|
||||
/* nvm_access definition and its masks/shifts need to be accessible to
|
||||
|
Loading…
Reference in New Issue
Block a user