forked from Minki/linux
clk: qcom: Add SDM660 GPU Clock Controller (GPUCC) driver
The GPUCC manages the clocks for the Adreno GPU found on the SDM630, SDM636, SDM660 SoCs. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210113183817.447866-9-angelogioacchino.delregno@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
AngeloGioacchino Del Regno
Stephen Boyd
parent
eaf87e5661
commit
79b5d1fc93
@ -401,6 +401,15 @@ config SDM_MMCC_660
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Say Y if you want to support multimedia devices such as display,
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graphics, video encode/decode, camera, etc.
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config SDM_GPUCC_660
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tristate "SDM660 Graphics Clock Controller"
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select SDM_GCC_660
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select QCOM_GDSC
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help
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Support for the graphics clock controller on SDM630/636/660 devices.
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Say Y if you want to support graphics controller devices and
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functionality such as 3D graphics
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config QCS_TURING_404
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tristate "QCS404 Turing Clock Controller"
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help
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@ -66,6 +66,7 @@ obj-$(CONFIG_SDM_CAMCC_845) += camcc-sdm845.o
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obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o
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obj-$(CONFIG_SDM_GCC_660) += gcc-sdm660.o
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obj-$(CONFIG_SDM_MMCC_660) += mmcc-sdm660.o
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obj-$(CONFIG_SDM_GPUCC_660) += gpucc-sdm660.o
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obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
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obj-$(CONFIG_SDM_GPUCC_845) += gpucc-sdm845.o
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obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o
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349
drivers/clk/qcom/gpucc-sdm660.c
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349
drivers/clk/qcom/gpucc-sdm660.c
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@ -0,0 +1,349 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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* Copyright (c) 2020, AngeloGioacchino Del Regno
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* <angelogioacchino.delregno@somainline.org>
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*/
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/regmap.h>
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#include <linux/reset-controller.h>
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#include <dt-bindings/clock/qcom,gpucc-sdm660.h>
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#include "clk-alpha-pll.h"
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#include "common.h"
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#include "clk-regmap.h"
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#include "clk-pll.h"
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#include "clk-rcg.h"
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#include "clk-branch.h"
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#include "gdsc.h"
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#include "reset.h"
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enum {
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P_GPU_XO,
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P_CORE_BI_PLL_TEST_SE,
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P_GPLL0_OUT_MAIN,
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P_GPLL0_OUT_MAIN_DIV,
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P_GPU_PLL0_PLL_OUT_MAIN,
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P_GPU_PLL1_PLL_OUT_MAIN,
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};
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static struct clk_branch gpucc_cxo_clk = {
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.halt_reg = 0x1020,
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.clkr = {
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.enable_reg = 0x1020,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpucc_cxo_clk",
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.parent_data = &(const struct clk_parent_data){
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.fw_name = "xo",
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.name = "xo"
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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.flags = CLK_IS_CRITICAL,
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},
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},
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};
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static struct pll_vco gpu_vco[] = {
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{ 1000000000, 2000000000, 0 },
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{ 500000000, 1000000000, 2 },
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{ 250000000, 500000000, 3 },
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};
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static struct clk_alpha_pll gpu_pll0_pll_out_main = {
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.offset = 0x0,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.vco_table = gpu_vco,
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.num_vco = ARRAY_SIZE(gpu_vco),
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpu_pll0_pll_out_main",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gpucc_cxo_clk.clkr.hw,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_ops,
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},
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};
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static struct clk_alpha_pll gpu_pll1_pll_out_main = {
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.offset = 0x40,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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.vco_table = gpu_vco,
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.num_vco = ARRAY_SIZE(gpu_vco),
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpu_pll1_pll_out_main",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gpucc_cxo_clk.clkr.hw,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_ops,
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},
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};
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static const struct parent_map gpucc_parent_map_1[] = {
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{ P_GPU_XO, 0 },
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{ P_GPU_PLL0_PLL_OUT_MAIN, 1 },
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{ P_GPU_PLL1_PLL_OUT_MAIN, 3 },
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{ P_GPLL0_OUT_MAIN, 5 },
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};
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static const struct clk_parent_data gpucc_parent_data_1[] = {
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{ .hw = &gpucc_cxo_clk.clkr.hw },
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{ .hw = &gpu_pll0_pll_out_main.clkr.hw },
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{ .hw = &gpu_pll1_pll_out_main.clkr.hw },
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{ .fw_name = "gcc_gpu_gpll0_clk", .name = "gcc_gpu_gpll0_clk" },
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};
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static struct clk_rcg2_gfx3d gfx3d_clk_src = {
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.div = 2,
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.rcg = {
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.cmd_rcgr = 0x1070,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = gpucc_parent_map_1,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gfx3d_clk_src",
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.parent_data = gpucc_parent_data_1,
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.num_parents = 4,
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.ops = &clk_gfx3d_ops,
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.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
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},
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},
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.hws = (struct clk_hw*[]){
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&gpucc_cxo_clk.clkr.hw,
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&gpu_pll0_pll_out_main.clkr.hw,
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&gpu_pll1_pll_out_main.clkr.hw,
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}
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};
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static struct clk_branch gpucc_gfx3d_clk = {
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.halt_reg = 0x1098,
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.halt_check = BRANCH_HALT,
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.hwcg_reg = 0x1098,
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.hwcg_bit = 1,
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.clkr = {
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.enable_reg = 0x1098,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpucc_gfx3d_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gfx3d_clk_src.rcg.clkr.hw,
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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},
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};
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static const struct parent_map gpucc_parent_map_0[] = {
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{ P_GPU_XO, 0 },
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{ P_GPLL0_OUT_MAIN, 5 },
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{ P_GPLL0_OUT_MAIN_DIV, 6 },
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};
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static const struct clk_parent_data gpucc_parent_data_0[] = {
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{ .hw = &gpucc_cxo_clk.clkr.hw },
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{ .fw_name = "gcc_gpu_gpll0_clk", .name = "gcc_gpu_gpll0_clk" },
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{ .fw_name = "gcc_gpu_gpll0_div_clk", .name = "gcc_gpu_gpll0_div_clk" },
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};
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static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = {
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F(19200000, P_GPU_XO, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 rbbmtimer_clk_src = {
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.cmd_rcgr = 0x10b0,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = gpucc_parent_map_0,
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.freq_tbl = ftbl_rbbmtimer_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "rbbmtimer_clk_src",
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.parent_data = gpucc_parent_data_0,
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.num_parents = 3,
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.ops = &clk_rcg2_ops,
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},
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};
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static const struct freq_tbl ftbl_rbcpr_clk_src[] = {
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F(19200000, P_GPU_XO, 1, 0, 0),
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F(50000000, P_GPLL0_OUT_MAIN_DIV, 6, 0, 0),
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{ }
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};
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static struct clk_rcg2 rbcpr_clk_src = {
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.cmd_rcgr = 0x1030,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = gpucc_parent_map_0,
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.freq_tbl = ftbl_rbcpr_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "rbcpr_clk_src",
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.parent_data = gpucc_parent_data_0,
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.num_parents = 3,
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.ops = &clk_rcg2_ops,
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},
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};
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static struct clk_branch gpucc_rbbmtimer_clk = {
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.halt_reg = 0x10d0,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x10d0,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpucc_rbbmtimer_clk",
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.parent_names = (const char *[]){
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"rbbmtimer_clk_src",
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpucc_rbcpr_clk = {
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.halt_reg = 0x1054,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1054,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpucc_rbcpr_clk",
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.parent_names = (const char *[]){
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"rbcpr_clk_src",
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct gdsc gpu_cx_gdsc = {
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.gdscr = 0x1004,
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.gds_hw_ctrl = 0x1008,
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.pd = {
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.name = "gpu_cx",
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},
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.pwrsts = PWRSTS_OFF_ON,
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.flags = VOTABLE,
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};
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static struct gdsc gpu_gx_gdsc = {
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.gdscr = 0x1094,
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.clamp_io_ctrl = 0x130,
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.resets = (unsigned int []){ GPU_GX_BCR },
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.reset_count = 1,
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.cxcs = (unsigned int []){ 0x1098 },
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.cxc_count = 1,
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.pd = {
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.name = "gpu_gx",
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},
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.parent = &gpu_cx_gdsc.pd,
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.pwrsts = PWRSTS_OFF | PWRSTS_ON | PWRSTS_RET,
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.flags = CLAMP_IO | SW_RESET | AON_RESET | NO_RET_PERIPH,
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};
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static struct gdsc *gpucc_sdm660_gdscs[] = {
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[GPU_CX_GDSC] = &gpu_cx_gdsc,
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[GPU_GX_GDSC] = &gpu_gx_gdsc,
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};
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static const struct qcom_reset_map gpucc_sdm660_resets[] = {
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[GPU_CX_BCR] = { 0x1000 },
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[RBCPR_BCR] = { 0x1050 },
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[GPU_GX_BCR] = { 0x1090 },
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[SPDM_BCR] = { 0x10E0 },
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};
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static struct clk_regmap *gpucc_sdm660_clocks[] = {
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[GPUCC_CXO_CLK] = &gpucc_cxo_clk.clkr,
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[GPU_PLL0_PLL] = &gpu_pll0_pll_out_main.clkr,
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[GPU_PLL1_PLL] = &gpu_pll1_pll_out_main.clkr,
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[GFX3D_CLK_SRC] = &gfx3d_clk_src.rcg.clkr,
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[RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
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[RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
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[GPUCC_RBCPR_CLK] = &gpucc_rbcpr_clk.clkr,
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[GPUCC_GFX3D_CLK] = &gpucc_gfx3d_clk.clkr,
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[GPUCC_RBBMTIMER_CLK] = &gpucc_rbbmtimer_clk.clkr,
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};
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static const struct regmap_config gpucc_660_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0x9034,
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.fast_io = true,
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};
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static const struct qcom_cc_desc gpucc_sdm660_desc = {
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.config = &gpucc_660_regmap_config,
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.clks = gpucc_sdm660_clocks,
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.num_clks = ARRAY_SIZE(gpucc_sdm660_clocks),
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.resets = gpucc_sdm660_resets,
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.num_resets = ARRAY_SIZE(gpucc_sdm660_resets),
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.gdscs = gpucc_sdm660_gdscs,
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.num_gdscs = ARRAY_SIZE(gpucc_sdm660_gdscs),
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};
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static const struct of_device_id gpucc_sdm660_match_table[] = {
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{ .compatible = "qcom,gpucc-sdm660" },
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{ .compatible = "qcom,gpucc-sdm630" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, gpucc_sdm660_match_table);
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static int gpucc_sdm660_probe(struct platform_device *pdev)
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{
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struct regmap *regmap;
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struct alpha_pll_config gpu_pll_config = {
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.config_ctl_val = 0x4001055b,
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.alpha = 0xaaaaab00,
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.alpha_en_mask = BIT(24),
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.vco_val = 0x2 << 20,
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.vco_mask = 0x3 << 20,
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.main_output_mask = 0x1,
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};
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regmap = qcom_cc_map(pdev, &gpucc_sdm660_desc);
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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/* 800MHz configuration for GPU PLL0 */
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gpu_pll_config.l = 0x29;
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gpu_pll_config.alpha_hi = 0xaa;
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clk_alpha_pll_configure(&gpu_pll0_pll_out_main, regmap, &gpu_pll_config);
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/* 740MHz configuration for GPU PLL1 */
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gpu_pll_config.l = 0x26;
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gpu_pll_config.alpha_hi = 0x8a;
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clk_alpha_pll_configure(&gpu_pll1_pll_out_main, regmap, &gpu_pll_config);
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return qcom_cc_really_probe(pdev, &gpucc_sdm660_desc, regmap);
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}
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static struct platform_driver gpucc_sdm660_driver = {
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.probe = gpucc_sdm660_probe,
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.driver = {
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.name = "gpucc-sdm660",
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.of_match_table = gpucc_sdm660_match_table,
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},
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};
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module_platform_driver(gpucc_sdm660_driver);
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MODULE_DESCRIPTION("Qualcomm SDM630/SDM660 GPUCC Driver");
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MODULE_LICENSE("GPL v2");
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28
include/dt-bindings/clock/qcom,gpucc-sdm660.h
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28
include/dt-bindings/clock/qcom,gpucc-sdm660.h
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@ -0,0 +1,28 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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* Copyright (c) 2020, AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
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*/
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#ifndef _DT_BINDINGS_CLK_SDM_GPUCC_660_H
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#define _DT_BINDINGS_CLK_SDM_GPUCC_660_H
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#define GPUCC_CXO_CLK 0
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#define GPU_PLL0_PLL 1
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#define GPU_PLL1_PLL 2
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#define GFX3D_CLK_SRC 3
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#define RBCPR_CLK_SRC 4
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#define RBBMTIMER_CLK_SRC 5
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#define GPUCC_RBCPR_CLK 6
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#define GPUCC_GFX3D_CLK 7
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#define GPUCC_RBBMTIMER_CLK 8
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#define GPU_CX_GDSC 0
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#define GPU_GX_GDSC 1
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#define GPU_CX_BCR 0
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#define GPU_GX_BCR 1
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#define RBCPR_BCR 2
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#define SPDM_BCR 3
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#endif
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