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clk: qcom: gdsc: add support for collapse-vote registers

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Recent Qualcomm platforms have APCS collapse-vote registers that allow
for sharing GDSCs with other masters (e.g. LPASS).

Add support for using such vote registers instead of the control
register when updating the GDSC power state.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220520100948.19622-3-johan+linaro@kernel.org
This commit is contained in:
Johan Hovold
2022-05-20 12:09:47 +02:00
committed by Bjorn Andersson
parent e73cb8527c
commit 77ea2bd72d
2 changed files with 11 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
drivers/clk/qcom/gdsc.c
View File

@@ -137,8 +137,13 @@ static int gdsc_update_collapse_bit(struct gdsc *sc, bool val)
u32 reg, mask;
int ret;
reg = sc->gdscr;
mask = SW_COLLAPSE_MASK;
if (sc->collapse_mask) {
reg = sc->collapse_ctrl;
mask = sc->collapse_mask;
} else {
reg = sc->gdscr;
mask = SW_COLLAPSE_MASK;
}
ret = regmap_update_bits(sc->regmap, reg, mask, val ? mask : 0);
if (ret)

4
drivers/clk/qcom/gdsc.h
View File

@@ -18,6 +18,8 @@ struct reset_controller_dev;
* @pd: generic power domain
* @regmap: regmap for MMIO accesses
* @gdscr: gsdc control register
* @collapse_ctrl: APCS collapse-vote register
* @collapse_mask: APCS collapse-vote mask
* @gds_hw_ctrl: gds_hw_ctrl register
* @cxcs: offsets of branch registers to toggle mem/periph bits in
* @cxc_count: number of @cxcs
@@ -35,6 +37,8 @@ struct gdsc {
struct generic_pm_domain *parent;
struct regmap *regmap;
unsigned int gdscr;
unsigned int collapse_ctrl;
unsigned int collapse_mask;
unsigned int gds_hw_ctrl;
unsigned int clamp_io_ctrl;
unsigned int *cxcs;