AT91 SoC for 5.20
It contains updates for integration with OP-TEE by having a dummy outer_cache.write_sec function to avoid triggering exception when Linux tries to update secure registers. -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQTsZ8eserC1pmhwqDmejrg/N2X7/QUCYtkKkAAKCRCejrg/N2X7 /daRAP4+Xhqo21g5cX+/TS4/DsjYSrMRdiMpCE2KaoLY/ON2GgD/bSN4ZW/nf40y NQgTNPK/b6d2/RsEzLaF+U1eb6Ag6Ag= =BiKA -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmLZTawACgkQmmx57+YA GNnnuA/+NKrf+D3F5lVF4FKavqBvX0vt1QjJVC2HN+eVTLhTGwIEKbvoxRrv2yEu 6hafPxpv8Tq0NO7oBQ9I/K9h4xJjgreI+CuIBExLe2NN6OCaVSjUrHfLU8ljCcyA +AsGShjoMieT1bljMWq28AKPJ0xXIwEVY/sz1NRhXo1BmKu//k0QTeI19a2MD4xP C7EB2colgENWPX4SR+/MEMr3GLOPy0zELSq1iOi4yUtxCd/PKoIkFogG4RsbDS07 QyLBm0Zwh+9UDd+7KaZJLSaxCZyHtv/M1hG/b7dlixLyypmPK4gg6+RXnzLmApMT VDF5Yon9rdr3Z26qkmoBQ3k9VAXe9VH1zY9fbAXDtqVE1MzmY5jAsOFk7n0lQrm9 dT7i7ZCfi/7lROEZ8l2XXalslf6Hl/IZB/VCX1WZ9BLt6HQNiafvzAbcpCFUyAQt I+H2Qfpbdi9R/OQkQBJZZy2Buip0NqE6VEXqAECmwSb3ySPJw9y6GMXiH08d6+pY nBUuC9fjsfusL2ZWQJojtPrsAyZL0Iq8l0rjR1Ntmq72EbqNRkWMG63zsQuAc2aR 2R1ZO3evyNxefEMQl3cD8yzOAJNtB8wrHc8t/BRr/Xu8cUP8x2e15I0uUwemOvFB l6e7xWUmRQPWWfDEShmb/Ph91N29PLa8prPekZp9JCVs2oAT3WQ= =ND2S -----END PGP SIGNATURE----- Merge tag 'at91-soc-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/soc AT91 SoC for 5.20 It contains updates for integration with OP-TEE by having a dummy outer_cache.write_sec function to avoid triggering exception when Linux tries to update secure registers. * tag 'at91-soc-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: ARM: at91: setup outer cache .write_sec() callback if needed ARM: at91: add sam_linux_is_optee_available() function Link: https://lore.kernel.org/r/20220721085852.1740924-1-claudiu.beznea@microchip.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
755d0ebc03
@ -27,6 +27,12 @@ struct arm_smccc_res sam_smccc_call(u32 fn, u32 arg0, u32 arg1)
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return res;
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}
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bool sam_linux_is_optee_available(void)
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{
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/* If optee has been detected, then we are running in normal world */
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return optee_available;
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}
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void __init sam_secure_init(void)
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{
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struct device_node *np;
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@ -14,5 +14,6 @@
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void __init sam_secure_init(void);
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struct arm_smccc_res sam_smccc_call(u32 fn, u32 arg0, u32 arg1);
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bool sam_linux_is_optee_available(void);
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#endif /* SAM_SECURE_H */
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@ -9,13 +9,27 @@
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/outercache.h>
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#include <asm/system_misc.h>
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#include "generic.h"
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#include "sam_secure.h"
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static void sama5_l2c310_write_sec(unsigned long val, unsigned reg)
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{
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/* OP-TEE configures the L2 cache and does not allow modifying it yet */
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}
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static void __init sama5_secure_cache_init(void)
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{
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sam_secure_init();
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if (sam_linux_is_optee_available())
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outer_cache.write_sec = sama5_l2c310_write_sec;
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}
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static void __init sama5_dt_device_init(void)
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{
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of_platform_default_populate(NULL, NULL, NULL);
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@ -48,7 +62,6 @@ MACHINE_END
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static void __init sama5d2_init(void)
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{
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of_platform_default_populate(NULL, NULL, NULL);
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sam_secure_init();
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sama5d2_pm_init();
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}
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@ -60,6 +73,7 @@ static const char *const sama5d2_compat[] __initconst = {
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DT_MACHINE_START(sama5d2, "Atmel SAMA5")
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/* Maintainer: Atmel */
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.init_machine = sama5d2_init,
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.init_early = sama5_secure_cache_init,
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.dt_compat = sama5d2_compat,
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.l2c_aux_mask = ~0UL,
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MACHINE_END
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