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MIPS: RM7000: Add support for tertiary cache

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Add support for the external T-cache interface. Allow for platform
independent size probing from 512KB to 8MB in powers of two.

Signed-off-by: Ricardo Mendoza <ricmm@gentoo.org>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1477/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ricardo Mendoza 2010-07-19 05:00:00 +01:00 committed by Ralf Baechle
parent 58a6d45193
commit 745aef5df1
2 changed files with 128 additions and 21 deletions
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2
arch/mips/include/asm/cacheops.h
View File

@ -62,6 +62,8 @@
* RM7000-specific cacheops
*/
#define Page_Invalidate_T 0x16
#define Index_Store_Tag_T 0x0a
#define Index_Load_Tag_T 0x06
/*
* R10000-specific cacheops

147
arch/mips/mm/sc-rm7k.c
View File

@ -16,6 +16,7 @@
#include <asm/cacheops.h>
#include <asm/mipsregs.h>
#include <asm/processor.h>
#include <asm/sections.h>
#include <asm/cacheflush.h> /* for run_uncached() */
/* Primary cache parameters. */
@ -25,11 +26,15 @@
/* Secondary cache parameters. */
#define scache_size (256*1024) /* Fixed to 256KiB on RM7000 */
/* Tertiary cache parameters */
#define tc_lsize 32
extern unsigned long icache_way_size, dcache_way_size;
unsigned long tcache_size;
#include <asm/r4kcache.h>
static int rm7k_tcache_enabled;
static int rm7k_tcache_init;
/*
* Writeback and invalidate the primary cache dcache before DMA.
@ -46,7 +51,7 @@ static void rm7k_sc_wback_inv(unsigned long addr, unsigned long size)
blast_scache_range(addr, addr + size);
if (!rm7k_tcache_enabled)
if (!rm7k_tcache_init)
return;
a = addr & ~(tc_pagesize - 1);
@ -70,7 +75,7 @@ static void rm7k_sc_inv(unsigned long addr, unsigned long size)
blast_inv_scache_range(addr, addr + size);
if (!rm7k_tcache_enabled)
if (!rm7k_tcache_init)
return;
a = addr & ~(tc_pagesize - 1);
@ -83,6 +88,45 @@ static void rm7k_sc_inv(unsigned long addr, unsigned long size)
}
}
static void blast_rm7k_tcache(void)
{
unsigned long start = CKSEG0ADDR(0);
unsigned long end = start + tcache_size;
write_c0_taglo(0);
while (start < end) {
cache_op(Page_Invalidate_T, start);
start += tc_pagesize;
}
}
/*
* This function is executed in uncached address space.
*/
static __cpuinit void __rm7k_tc_enable(void)
{
int i;
set_c0_config(RM7K_CONF_TE);
write_c0_taglo(0);
write_c0_taghi(0);
for (i = 0; i < tcache_size; i += tc_lsize)
cache_op(Index_Store_Tag_T, CKSEG0ADDR(i));
}
static __cpuinit void rm7k_tc_enable(void)
{
if (read_c0_config() & RM7K_CONF_TE)
return;
BUG_ON(tcache_size == 0);
run_uncached(__rm7k_tc_enable);
}
/*
* This function is executed in uncached address space.
*/
@ -104,13 +148,29 @@ static __cpuinit void rm7k_sc_enable(void)
if (read_c0_config() & RM7K_CONF_SE)
return;
printk(KERN_INFO "Enabling secondary cache...\n");
pr_info("Enabling secondary cache...\n");
run_uncached(__rm7k_sc_enable);
if (rm7k_tcache_init)
rm7k_tc_enable();
}
static void rm7k_tc_disable(void)
{
unsigned long flags;
local_irq_save(flags);
blast_rm7k_tcache();
clear_c0_config(RM7K_CONF_TE);
local_irq_save(flags);
}
static void rm7k_sc_disable(void)
{
clear_c0_config(RM7K_CONF_SE);
if (rm7k_tcache_init)
rm7k_tc_disable();
}
static struct bcache_ops rm7k_sc_ops = {
@ -120,6 +180,52 @@ static struct bcache_ops rm7k_sc_ops = {
.bc_inv = rm7k_sc_inv
};
/*
* This is a probing function like the one found in c-r4k.c, we look for the
* wrap around point with different addresses.
*/
static __cpuinit void __probe_tcache(void)
{
unsigned long flags, addr, begin, end, pow2;
begin = (unsigned long) &_stext;
begin &= ~((8 * 1024 * 1024) - 1);
end = begin + (8 * 1024 * 1024);
local_irq_save(flags);
set_c0_config(RM7K_CONF_TE);
/* Fill size-multiple lines with a valid tag */
pow2 = (256 * 1024);
for (addr = begin; addr <= end; addr = (begin + pow2)) {
unsigned long *p = (unsigned long *) addr;
__asm__ __volatile__("nop" : : "r" (*p));
pow2 <<= 1;
}
/* Load first line with a 0 tag, to check after */
write_c0_taglo(0);
write_c0_taghi(0);
cache_op(Index_Store_Tag_T, begin);
/* Look for the wrap-around */
pow2 = (512 * 1024);
for (addr = begin + (512 * 1024); addr <= end; addr = begin + pow2) {
cache_op(Index_Load_Tag_T, addr);
if (!read_c0_taglo())
break;
pow2 <<= 1;
}
addr -= begin;
tcache_size = addr;
clear_c0_config(RM7K_CONF_TE);
local_irq_restore(flags);
}
void __cpuinit rm7k_sc_init(void)
{
struct cpuinfo_mips *c = &current_cpu_data;
@ -139,27 +245,26 @@ void __cpuinit rm7k_sc_init(void)
if (!(config & RM7K_CONF_SE))
rm7k_sc_enable();
bcops = &rm7k_sc_ops;
/*
* While we're at it let's deal with the tertiary cache.
*/
if (!(config & RM7K_CONF_TC)) {
/*
* We can't enable the L3 cache yet. There may be board-specific
* magic necessary to turn it on, and blindly asking the CPU to
* start using it would may give cache errors.
*
* Also, board-specific knowledge may allow us to use the
* CACHE Flash_Invalidate_T instruction if the tag RAM supports
* it, and may specify the size of the L3 cache so we don't have
* to probe it.
*/
printk(KERN_INFO "Tertiary cache present, %s enabled\n",
(config & RM7K_CONF_TE) ? "already" : "not (yet)");
rm7k_tcache_init = 0;
tcache_size = 0;
if ((config & RM7K_CONF_TE))
rm7k_tcache_enabled = 1;
}
if (config & RM7K_CONF_TC)
return;
bcops = &rm7k_sc_ops;
/*
* No efficient way to ask the hardware for the size of the tcache,
* so must probe for it.
*/
run_uncached(__probe_tcache);
rm7k_tc_enable();
rm7k_tcache_init = 1;
c->tcache.linesz = tc_lsize;
c->tcache.ways = 1;
pr_info("Tertiary cache size %ldK.\n", (tcache_size >> 10));
}