forked from Minki/linux
drm/i915: Build workaround list in ring initialization
If we build the workaround list in ring initialization and decouple it from the actual writing of values, we gain the ability to decide where and how we want to apply the values. The advantage of this will become more clear when we need to initialize workarounds on older gens where it is not possible to write all the registers through ring LRIs. v2: rebase on newest bdw workarounds Cc: Arun Siluvery <arun.siluvery@linux.intel.com> Cc: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com> [danvet: Resolve tiny conflict in comments and ocd alignments a bit.] [danvet2: Remove bogus force_wake_get call spotted by Paulo and QA.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Mika Kuoppala
Daniel Vetter
parent
8eff426233
commit
7225342ab5
@ -2655,18 +2655,18 @@ static int i915_wa_registers(struct seq_file *m, void *unused)
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intel_runtime_pm_get(dev_priv);
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seq_printf(m, "Workarounds applied: %d\n", dev_priv->num_wa_regs);
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for (i = 0; i < dev_priv->num_wa_regs; ++i) {
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seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
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for (i = 0; i < dev_priv->workarounds.count; ++i) {
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u32 addr, mask;
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addr = dev_priv->intel_wa_regs[i].addr;
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mask = dev_priv->intel_wa_regs[i].mask;
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dev_priv->intel_wa_regs[i].value = I915_READ(addr) | mask;
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if (dev_priv->intel_wa_regs[i].addr)
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addr = dev_priv->workarounds.reg[i].addr;
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mask = dev_priv->workarounds.reg[i].mask;
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dev_priv->workarounds.reg[i].value = I915_READ(addr) | mask;
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if (dev_priv->workarounds.reg[i].addr)
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seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n",
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dev_priv->intel_wa_regs[i].addr,
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dev_priv->intel_wa_regs[i].value,
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dev_priv->intel_wa_regs[i].mask);
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dev_priv->workarounds.reg[i].addr,
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dev_priv->workarounds.reg[i].value,
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dev_priv->workarounds.reg[i].mask);
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}
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intel_runtime_pm_put(dev_priv);
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@ -1448,6 +1448,20 @@ struct i915_frontbuffer_tracking {
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unsigned flip_bits;
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};
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struct i915_wa_reg {
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u32 addr;
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u32 value;
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/* bitmask representing WA bits */
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u32 mask;
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};
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#define I915_MAX_WA_REGS 16
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struct i915_workarounds {
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struct i915_wa_reg reg[I915_MAX_WA_REGS];
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u32 count;
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};
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struct drm_i915_private {
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struct drm_device *dev;
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struct kmem_cache *slab;
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@ -1590,19 +1604,7 @@ struct drm_i915_private {
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struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
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int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
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/*
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* workarounds are currently applied at different places and
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* changes are being done to consolidate them so exact count is
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* not clear at this point, use a max value for now.
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*/
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#define I915_MAX_WA_REGS 16
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struct {
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u32 addr;
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u32 value;
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/* bitmask representing WA bits */
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u32 mask;
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} intel_wa_regs[I915_MAX_WA_REGS];
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u32 num_wa_regs;
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struct i915_workarounds workarounds;
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/* Reclocking support */
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bool render_reclock_avail;
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@ -665,79 +665,107 @@ err:
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return ret;
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}
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static inline void intel_ring_emit_wa(struct intel_engine_cs *ring,
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u32 addr, u32 value)
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static int intel_ring_workarounds_emit(struct intel_engine_cs *ring)
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{
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int ret, i;
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struct drm_device *dev = ring->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct i915_workarounds *w = &dev_priv->workarounds;
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if (WARN_ON(dev_priv->num_wa_regs >= I915_MAX_WA_REGS))
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return;
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if (WARN_ON(w->count == 0))
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return 0;
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intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
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intel_ring_emit(ring, addr);
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intel_ring_emit(ring, value);
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dev_priv->intel_wa_regs[dev_priv->num_wa_regs].addr = addr;
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dev_priv->intel_wa_regs[dev_priv->num_wa_regs].mask = value & 0xFFFF;
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/* value is updated with the status of remaining bits of this
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* register when it is read from debugfs file
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*/
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dev_priv->intel_wa_regs[dev_priv->num_wa_regs].value = value;
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dev_priv->num_wa_regs++;
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return;
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}
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static int bdw_init_workarounds(struct intel_engine_cs *ring)
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{
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int ret;
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struct drm_device *dev = ring->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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/*
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* workarounds applied in this fn are part of register state context,
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* they need to be re-initialized followed by gpu reset, suspend/resume,
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* module reload.
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*/
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dev_priv->num_wa_regs = 0;
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memset(dev_priv->intel_wa_regs, 0, sizeof(dev_priv->intel_wa_regs));
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/*
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* update the number of dwords required based on the
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* actual number of workarounds applied
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*/
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ret = intel_ring_begin(ring, 18);
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ring->gpu_caches_dirty = true;
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ret = intel_ring_flush_all_caches(ring);
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if (ret)
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return ret;
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ret = intel_ring_begin(ring, w->count * 3);
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if (ret)
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return ret;
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for (i = 0; i < w->count; i++) {
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intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
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intel_ring_emit(ring, w->reg[i].addr);
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intel_ring_emit(ring, w->reg[i].value);
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}
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intel_ring_advance(ring);
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ring->gpu_caches_dirty = true;
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ret = intel_ring_flush_all_caches(ring);
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if (ret)
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return ret;
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DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
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return 0;
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}
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static int wa_add(struct drm_i915_private *dev_priv,
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const u32 addr, const u32 val, const u32 mask)
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{
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const u32 idx = dev_priv->workarounds.count;
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if (WARN_ON(idx >= I915_MAX_WA_REGS))
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return -ENOSPC;
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dev_priv->workarounds.reg[idx].addr = addr;
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dev_priv->workarounds.reg[idx].value = val;
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dev_priv->workarounds.reg[idx].mask = mask;
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dev_priv->workarounds.count++;
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return 0;
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}
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#define WA_REG(addr, val, mask) { \
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const int r = wa_add(dev_priv, (addr), (val), (mask)); \
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if (r) \
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return r; \
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}
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#define WA_SET_BIT_MASKED(addr, mask) \
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WA_REG(addr, _MASKED_BIT_ENABLE(mask), (mask) & 0xffff)
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#define WA_CLR_BIT_MASKED(addr, mask) \
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WA_REG(addr, _MASKED_BIT_DISABLE(mask), (mask) & 0xffff)
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#define WA_SET_BIT(addr, mask) WA_REG(addr, I915_READ(addr) | (mask), mask)
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#define WA_CLR_BIT(addr, mask) WA_REG(addr, I915_READ(addr) & ~(mask), mask)
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#define WA_WRITE(addr, val) WA_REG(addr, val, 0xffffffff)
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static int bdw_init_workarounds(struct intel_engine_cs *ring)
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{
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struct drm_device *dev = ring->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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/* WaDisablePartialInstShootdown:bdw */
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/* WaDisableThreadStallDopClockGating:bdw (pre-production) */
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intel_ring_emit_wa(ring, GEN8_ROW_CHICKEN,
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_MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
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| STALL_DOP_GATING_DISABLE));
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WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
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PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
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STALL_DOP_GATING_DISABLE);
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/* WaDisableDopClockGating:bdw */
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intel_ring_emit_wa(ring, GEN7_ROW_CHICKEN2,
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_MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
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WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
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DOP_CLOCK_GATING_DISABLE);
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intel_ring_emit_wa(ring, HALF_SLICE_CHICKEN3,
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_MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
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WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
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GEN8_SAMPLER_POWER_BYPASS_DIS);
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/* Use Force Non-Coherent whenever executing a 3D context. This is a
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* workaround for for a possible hang in the unlikely event a TLB
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* invalidation occurs during a PSD flush.
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*/
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/* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */
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intel_ring_emit_wa(ring, HDC_CHICKEN0,
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_MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT |
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(IS_BDW_GT3(dev) ?
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HDC_FENCE_DEST_SLM_DISABLE : 0)
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));
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WA_SET_BIT_MASKED(HDC_CHICKEN0,
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HDC_FORCE_NON_COHERENT |
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(IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
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/* Wa4x4STCOptimizationDisable:bdw */
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intel_ring_emit_wa(ring, CACHE_MODE_1,
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_MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
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WA_SET_BIT_MASKED(CACHE_MODE_1,
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GEN8_4x4_STC_OPTIMIZATION_DISABLE);
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/*
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* BSpec recommends 8x4 when MSAA is used,
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@ -747,52 +775,50 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
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* disable bit, which we don't touch here, but it's good
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* to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
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*/
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intel_ring_emit_wa(ring, GEN7_GT_MODE,
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GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
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intel_ring_advance(ring);
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DRM_DEBUG_DRIVER("Number of Workarounds applied: %d\n",
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dev_priv->num_wa_regs);
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WA_SET_BIT_MASKED(GEN7_GT_MODE,
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GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
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return 0;
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}
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static int chv_init_workarounds(struct intel_engine_cs *ring)
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{
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int ret;
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struct drm_device *dev = ring->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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/*
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* workarounds applied in this fn are part of register state context,
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* they need to be re-initialized followed by gpu reset, suspend/resume,
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* module reload.
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*/
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dev_priv->num_wa_regs = 0;
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memset(dev_priv->intel_wa_regs, 0, sizeof(dev_priv->intel_wa_regs));
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ret = intel_ring_begin(ring, 12);
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if (ret)
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return ret;
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/* WaDisablePartialInstShootdown:chv */
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intel_ring_emit_wa(ring, GEN8_ROW_CHICKEN,
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_MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
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WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
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PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
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/* WaDisableThreadStallDopClockGating:chv */
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intel_ring_emit_wa(ring, GEN8_ROW_CHICKEN,
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_MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
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WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
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STALL_DOP_GATING_DISABLE);
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/* WaDisableDopClockGating:chv (pre-production hw) */
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intel_ring_emit_wa(ring, GEN7_ROW_CHICKEN2,
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_MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
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WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
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DOP_CLOCK_GATING_DISABLE);
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/* WaDisableSamplerPowerBypass:chv (pre-production hw) */
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intel_ring_emit_wa(ring, HALF_SLICE_CHICKEN3,
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_MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
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WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
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GEN8_SAMPLER_POWER_BYPASS_DIS);
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intel_ring_advance(ring);
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return 0;
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}
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static int init_workarounds_ring(struct intel_engine_cs *ring)
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{
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struct drm_device *dev = ring->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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WARN_ON(ring->id != RCS);
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dev_priv->workarounds.count = 0;
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if (IS_BROADWELL(dev))
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return bdw_init_workarounds(ring);
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if (IS_CHERRYVIEW(dev))
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return chv_init_workarounds(ring);
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return 0;
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}
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@ -852,7 +878,7 @@ static int init_render_ring(struct intel_engine_cs *ring)
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if (HAS_L3_DPF(dev))
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I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
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return ret;
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return init_workarounds_ring(ring);
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}
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static void render_ring_cleanup(struct intel_engine_cs *ring)
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@ -2298,10 +2324,8 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
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dev_priv->semaphore_obj = obj;
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}
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}
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if (IS_CHERRYVIEW(dev))
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ring->init_context = chv_init_workarounds;
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else
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ring->init_context = bdw_init_workarounds;
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ring->init_context = intel_ring_workarounds_emit;
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ring->add_request = gen6_add_request;
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ring->flush = gen8_render_ring_flush;
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ring->irq_get = gen8_ring_get_irq;
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