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m68knommu: clean up use of MBAR for DRAM registers on ColdFire start

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In some of the RAM size autodetection code on ColdFire CPU startup
we reference DRAM registers relative to the MBAR register. Not all of
the supported ColdFire CPUs have an MBAR, and currently this works
because we fake an MBAR address on those registers. In an effort to
clean this up, and eventually remove the fake MBAR setting make the
DRAM register address definitions actually contain the MBAR (or IPSBAR
as appropriate) value as required.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
This commit is contained in:
Greg Ungerer 2011-03-06 23:01:46 +10:00
parent 58f0ac98f3
commit 6a92e1982d
8 changed files with 49 additions and 49 deletions
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16
arch/m68k/include/asm/m5206sim.h
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@ -48,14 +48,14 @@
#define MCFSIM_SWIVR 0x42 /* SW Watchdog intr reg (r/w) */
#define MCFSIM_SWSR 0x43 /* SW Watchdog service (r/w) */
#define MCFSIM_DCRR 0x46 /* DRAM Refresh reg (r/w) */
#define MCFSIM_DCTR 0x4a /* DRAM Timing reg (r/w) */
#define MCFSIM_DAR0 0x4c /* DRAM 0 Address reg(r/w) */
#define MCFSIM_DMR0 0x50 /* DRAM 0 Mask reg (r/w) */
#define MCFSIM_DCR0 0x57 /* DRAM 0 Control reg (r/w) */
#define MCFSIM_DAR1 0x58 /* DRAM 1 Address reg (r/w) */
#define MCFSIM_DMR1 0x5c /* DRAM 1 Mask reg (r/w) */
#define MCFSIM_DCR1 0x63 /* DRAM 1 Control reg (r/w) */
#define MCFSIM_DCRR (MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */
#define MCFSIM_DCTR (MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */
#define MCFSIM_DAR0 (MCF_MBAR + 0x4c) /* DRAM 0 Address reg(r/w) */
#define MCFSIM_DMR0 (MCF_MBAR + 0x50) /* DRAM 0 Mask reg (r/w) */
#define MCFSIM_DCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control reg (r/w) */
#define MCFSIM_DAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address reg (r/w) */
#define MCFSIM_DMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */
#define MCFSIM_DCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */
#define MCFSIM_CSAR0 0x64 /* CS 0 Address 0 reg (r/w) */
#define MCFSIM_CSMR0 0x68 /* CS 0 Mask 0 reg (r/w) */

10
arch/m68k/include/asm/m523xsim.h
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@ -40,11 +40,11 @@
/*
* SDRAM configuration registers.
*/
#define MCFSIM_DCR 0x44 /* SDRAM control */
#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */
#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */
#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */
#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */
#define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */
#define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */
#define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */
#define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */
#define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */
/*
* Reset Controll Unit (relative to IPSBAR).

10
arch/m68k/include/asm/m5249sim.h
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@ -60,11 +60,11 @@
#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */
#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */
#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */
#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */
#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */
#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */
/*
* Timer module.

26
arch/m68k/include/asm/m527xsim.h
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@ -43,21 +43,21 @@
* SDRAM configuration registers.
*/
#ifdef CONFIG_M5271
#define MCFSIM_DCR 0x40 /* SDRAM control */
#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */
#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */
#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */
#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */
#define MCFSIM_DCR (MCF_IPSBAR + 0x40) /* Control */
#define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */
#define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */
#define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */
#define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */
#endif
#ifdef CONFIG_M5275
#define MCFSIM_DMR 0x40 /* SDRAM mode */
#define MCFSIM_DCR 0x44 /* SDRAM control */
#define MCFSIM_DCFG1 0x48 /* SDRAM configuration 1 */
#define MCFSIM_DCFG2 0x4c /* SDRAM configuration 2 */
#define MCFSIM_DBAR0 0x50 /* SDRAM base address 0 */
#define MCFSIM_DMR0 0x54 /* SDRAM address mask 0 */
#define MCFSIM_DBAR1 0x58 /* SDRAM base address 1 */
#define MCFSIM_DMR1 0x5c /* SDRAM address mask 1 */
#define MCFSIM_DMR (MCF_IPSBAR + 0x40) /* Mode */
#define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */
#define MCFSIM_DCFG1 (MCF_IPSBAR + 0x48) /* Configuration 1 */
#define MCFSIM_DCFG2 (MCF_IPSBAR + 0x4c) /* Configuration 2 */
#define MCFSIM_DBAR0 (MCF_IPSBAR + 0x50) /* Base address 0 */
#define MCFSIM_DMR0 (MCF_IPSBAR + 0x54) /* Address mask 0 */
#define MCFSIM_DBAR1 (MCF_IPSBAR + 0x58) /* Base address 1 */
#define MCFSIM_DMR1 (MCF_IPSBAR + 0x5c) /* Address mask 1 */
#endif
/*

10
arch/m68k/include/asm/m528xsim.h
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@ -40,11 +40,11 @@
/*
* SDRAM configuration registers.
*/
#define MCFSIM_DCR 0x44 /* SDRAM control */
#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */
#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */
#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */
#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */
#define MCFSIM_DCR (MCF_IPSBAR + 0x00000044) /* Control */
#define MCFSIM_DACR0 (MCF_IPSBAR + 0x00000048) /* Base address 0 */
#define MCFSIM_DMR0 (MCF_IPSBAR + 0x0000004c) /* Address mask 0 */
#define MCFSIM_DACR1 (MCF_IPSBAR + 0x00000050) /* Base address 1 */
#define MCFSIM_DMR1 (MCF_IPSBAR + 0x00000054) /* Address mask 1 */
/*
* DMA unit base addresses.

10
arch/m68k/include/asm/m5307sim.h
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@ -89,11 +89,11 @@
#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */
#endif /* CONFIG_OLDMASK */
#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */
#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */
#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */
#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM Addr/Ctrl 0 */
#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM Mask 0 */
#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM Addr/Ctrl 1 */
#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM Mask 1 */
/*
* Timer module.

10
arch/m68k/include/asm/m5407sim.h
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@ -72,11 +72,11 @@
#define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */
#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */
#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */
#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */
#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */
#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */
#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */
#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */
/*
* Timer module.

6
arch/m68knommu/platform/coldfire/head.S
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@ -41,17 +41,17 @@
* DRAM controller is quite different.
*/
.macro GET_MEM_SIZE
movel MCF_MBAR+MCFSIM_DMR0,%d0 /* get mask for 1st bank */
movel MCFSIM_DMR0,%d0 /* get mask for 1st bank */
btst #0,%d0 /* check if region enabled */
beq 1f
andl #0xfffc0000,%d0
beq 1f
addl #0x00040000,%d0 /* convert mask to size */
1:
movel MCF_MBAR+MCFSIM_DMR1,%d1 /* get mask for 2nd bank */
movel MCFSIM_DMR1,%d1 /* get mask for 2nd bank */
btst #0,%d1 /* check if region enabled */
beq 2f
andl #0xfffc0000, %d1
andl #0xfffc0000,%d1
beq 2f
addl #0x00040000,%d1
addl %d1,%d0 /* total mem size in d0 */