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ARM: imx6: fix bogus use of irq_get_irq_data

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The imx6 PM code seems to be quite creative in its use of irq_data,
using something that is very much a hardware interrupt number where
we expect a virtual one.  Yes, it worked so far, but that's only
luck, and it will definitely explode in 3.19.

Fix it by using a pair of helper functions that deal with the
actual hardware.

Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Marc Zyngier 2014-12-02 16:05:26 +00:00 committed by Olof Johansson
parent e2fd06f6be
commit 65bb688aab
3 changed files with 26 additions and 17 deletions
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4
arch/arm/mach-imx/common.h
View File

@ -108,8 +108,8 @@ void imx_gpc_pre_suspend(bool arm_power_off);
void imx_gpc_post_resume(void);
void imx_gpc_mask_all(void);
void imx_gpc_restore_all(void);
void imx_gpc_irq_mask(struct irq_data *d);
void imx_gpc_irq_unmask(struct irq_data *d);
void imx_gpc_hwirq_mask(unsigned int hwirq);
void imx_gpc_hwirq_unmask(unsigned int hwirq);
void imx_anatop_init(void);
void imx_anatop_pre_suspend(void);
void imx_anatop_post_resume(void);

34
arch/arm/mach-imx/gpc.c
View File

@ -91,34 +91,44 @@ void imx_gpc_restore_all(void)
writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
}
void imx_gpc_irq_unmask(struct irq_data *d)
void imx_gpc_hwirq_unmask(unsigned int hwirq)
{
void __iomem *reg;
u32 val;
/* Sanity check for SPI irq */
if (d->hwirq < 32)
return;
reg = gpc_base + GPC_IMR1 + (d->hwirq / 32 - 1) * 4;
reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4;
val = readl_relaxed(reg);
val &= ~(1 << d->hwirq % 32);
val &= ~(1 << hwirq % 32);
writel_relaxed(val, reg);
}
void imx_gpc_irq_mask(struct irq_data *d)
void imx_gpc_hwirq_mask(unsigned int hwirq)
{
void __iomem *reg;
u32 val;
reg = gpc_base + GPC_IMR1 + (hwirq / 32 - 1) * 4;
val = readl_relaxed(reg);
val |= 1 << (hwirq % 32);
writel_relaxed(val, reg);
}
static void imx_gpc_irq_unmask(struct irq_data *d)
{
/* Sanity check for SPI irq */
if (d->hwirq < 32)
return;
reg = gpc_base + GPC_IMR1 + (d->hwirq / 32 - 1) * 4;
val = readl_relaxed(reg);
val |= 1 << (d->hwirq % 32);
writel_relaxed(val, reg);
imx_gpc_hwirq_unmask(d->hwirq);
}
static void imx_gpc_irq_mask(struct irq_data *d)
{
/* Sanity check for SPI irq */
if (d->hwirq < 32)
return;
imx_gpc_hwirq_mask(d->hwirq);
}
void __init imx_gpc_init(void)

5
arch/arm/mach-imx/pm-imx6.c
View File

@ -261,7 +261,6 @@ static void imx6q_enable_wb(bool enable)
int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
{
struct irq_data *iomuxc_irq_data = irq_get_irq_data(32);
u32 val = readl_relaxed(ccm_base + CLPCR);
val &= ~BM_CLPCR_LPM;
@ -316,9 +315,9 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
* 3) Software should mask IRQ #32 right after CCM Low-Power mode
* is set (set bits 0-1 of CCM_CLPCR).
*/
imx_gpc_irq_unmask(iomuxc_irq_data);
imx_gpc_hwirq_unmask(32);
writel_relaxed(val, ccm_base + CLPCR);
imx_gpc_irq_mask(iomuxc_irq_data);
imx_gpc_hwirq_mask(32);
return 0;
}