forked from Minki/linux
clk: sifive: Move all stuff into SoCs header files from C files
Improve PRCI driver to reduce the complexity, we remove the SoCs C files
by putting all stuff in each SoCs header files, and include these
SoCs-specific header files in core of PRCI. It can also avoid the W=1
kernel build warnings about variable defined but not used
[-Wunused-const-variable=], like commit 487dc7bb6a ("clk: sifive:
fu540-prci: Declare static const variable 'prci_clk_fu540' where it's
used") does.
Signed-off-by: Zong Li <zong.li@sifive.com>
Suggested-by: Lee Jones <lee.jones@linaro.org>
Reviewed-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Link: https://lore.kernel.org/r/a3c7ec5c46c1d8be455d1c347db4855bb56cec53.1646388139.git.zong.li@sifive.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Zong Li
Stephen Boyd
parent
24a4a29f75
commit
5e916932df
@ -1,2 +1,2 @@
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# SPDX-License-Identifier: GPL-2.0-only
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obj-$(CONFIG_CLK_SIFIVE_PRCI) += sifive-prci.o fu540-prci.o fu740-prci.o
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obj-$(CONFIG_CLK_SIFIVE_PRCI) += sifive-prci.o
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@ -1,88 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018-2022 SiFive, Inc.
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* Copyright (C) 2018-2019 Wesley Terpstra
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* Copyright (C) 2018-2019 Paul Walmsley
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* Copyright (C) 2020-2022 Zong Li
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*
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* The FU540 PRCI implements clock and reset control for the SiFive
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* FU540-C000 chip. This driver assumes that it has sole control
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* over all PRCI resources.
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*
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* This driver is based on the PRCI driver written by Wesley Terpstra:
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* https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d221b2ee56bb60
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*
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* References:
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* - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset"
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*/
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#include <linux/module.h>
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#include <dt-bindings/clock/sifive-fu540-prci.h>
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#include "sifive-prci.h"
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/* PRCI integration data for each WRPLL instance */
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static struct __prci_wrpll_data sifive_fu540_prci_corepll_data = {
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.cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
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.cfg1_offs = PRCI_COREPLLCFG1_OFFSET,
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.enable_bypass = sifive_prci_coreclksel_use_hfclk,
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.disable_bypass = sifive_prci_coreclksel_use_corepll,
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};
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static struct __prci_wrpll_data sifive_fu540_prci_ddrpll_data = {
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.cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
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.cfg1_offs = PRCI_DDRPLLCFG1_OFFSET,
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};
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static struct __prci_wrpll_data sifive_fu540_prci_gemgxlpll_data = {
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.cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
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.cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET,
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};
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/* Linux clock framework integration */
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static const struct clk_ops sifive_fu540_prci_wrpll_clk_ops = {
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.set_rate = sifive_prci_wrpll_set_rate,
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.round_rate = sifive_prci_wrpll_round_rate,
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.recalc_rate = sifive_prci_wrpll_recalc_rate,
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.enable = sifive_prci_clock_enable,
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.disable = sifive_prci_clock_disable,
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.is_enabled = sifive_clk_is_enabled,
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};
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static const struct clk_ops sifive_fu540_prci_wrpll_ro_clk_ops = {
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.recalc_rate = sifive_prci_wrpll_recalc_rate,
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};
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static const struct clk_ops sifive_fu540_prci_tlclksel_clk_ops = {
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.recalc_rate = sifive_prci_tlclksel_recalc_rate,
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};
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/* List of clock controls provided by the PRCI */
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struct __prci_clock __prci_init_clocks_fu540[] = {
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[FU540_PRCI_CLK_COREPLL] = {
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.name = "corepll",
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.parent_name = "hfclk",
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.ops = &sifive_fu540_prci_wrpll_clk_ops,
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.pwd = &sifive_fu540_prci_corepll_data,
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},
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[FU540_PRCI_CLK_DDRPLL] = {
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.name = "ddrpll",
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.parent_name = "hfclk",
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.ops = &sifive_fu540_prci_wrpll_ro_clk_ops,
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.pwd = &sifive_fu540_prci_ddrpll_data,
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},
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[FU540_PRCI_CLK_GEMGXLPLL] = {
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.name = "gemgxlpll",
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.parent_name = "hfclk",
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.ops = &sifive_fu540_prci_wrpll_clk_ops,
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.pwd = &sifive_fu540_prci_gemgxlpll_data,
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},
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[FU540_PRCI_CLK_TLCLK] = {
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.name = "tlclk",
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.parent_name = "corepll",
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.ops = &sifive_fu540_prci_tlclksel_clk_ops,
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},
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};
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@ -1,16 +1,99 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 SiFive, Inc.
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* Zong Li
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* Copyright (C) 2018-2021 SiFive, Inc.
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* Copyright (C) 2018-2019 Wesley Terpstra
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* Copyright (C) 2018-2019 Paul Walmsley
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* Copyright (C) 2020-2021 Zong Li
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*
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* The FU540 PRCI implements clock and reset control for the SiFive
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* FU540-C000 chip. This driver assumes that it has sole control
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* over all PRCI resources.
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*
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* This driver is based on the PRCI driver written by Wesley Terpstra:
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* https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d221b2ee56bb60
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*
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* References:
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* - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset"
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*/
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#ifndef __SIFIVE_CLK_FU540_PRCI_H
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#define __SIFIVE_CLK_FU540_PRCI_H
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#include <linux/module.h>
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#include <dt-bindings/clock/sifive-fu540-prci.h>
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#include "sifive-prci.h"
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#define NUM_CLOCK_FU540 4
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/* PRCI integration data for each WRPLL instance */
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extern struct __prci_clock __prci_init_clocks_fu540[NUM_CLOCK_FU540];
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static struct __prci_wrpll_data sifive_fu540_prci_corepll_data = {
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.cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
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.cfg1_offs = PRCI_COREPLLCFG1_OFFSET,
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.enable_bypass = sifive_prci_coreclksel_use_hfclk,
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.disable_bypass = sifive_prci_coreclksel_use_corepll,
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};
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static struct __prci_wrpll_data sifive_fu540_prci_ddrpll_data = {
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.cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
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.cfg1_offs = PRCI_DDRPLLCFG1_OFFSET,
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};
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static struct __prci_wrpll_data sifive_fu540_prci_gemgxlpll_data = {
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.cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
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.cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET,
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};
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/* Linux clock framework integration */
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static const struct clk_ops sifive_fu540_prci_wrpll_clk_ops = {
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.set_rate = sifive_prci_wrpll_set_rate,
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.round_rate = sifive_prci_wrpll_round_rate,
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.recalc_rate = sifive_prci_wrpll_recalc_rate,
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.enable = sifive_prci_clock_enable,
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.disable = sifive_prci_clock_disable,
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.is_enabled = sifive_clk_is_enabled,
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};
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static const struct clk_ops sifive_fu540_prci_wrpll_ro_clk_ops = {
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.recalc_rate = sifive_prci_wrpll_recalc_rate,
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};
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static const struct clk_ops sifive_fu540_prci_tlclksel_clk_ops = {
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.recalc_rate = sifive_prci_tlclksel_recalc_rate,
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};
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/* List of clock controls provided by the PRCI */
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static struct __prci_clock __prci_init_clocks_fu540[] = {
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[FU540_PRCI_CLK_COREPLL] = {
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.name = "corepll",
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.parent_name = "hfclk",
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.ops = &sifive_fu540_prci_wrpll_clk_ops,
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.pwd = &sifive_fu540_prci_corepll_data,
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},
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[FU540_PRCI_CLK_DDRPLL] = {
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.name = "ddrpll",
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.parent_name = "hfclk",
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.ops = &sifive_fu540_prci_wrpll_ro_clk_ops,
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.pwd = &sifive_fu540_prci_ddrpll_data,
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},
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[FU540_PRCI_CLK_GEMGXLPLL] = {
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.name = "gemgxlpll",
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.parent_name = "hfclk",
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.ops = &sifive_fu540_prci_wrpll_clk_ops,
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.pwd = &sifive_fu540_prci_gemgxlpll_data,
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},
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[FU540_PRCI_CLK_TLCLK] = {
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.name = "tlclk",
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.parent_name = "corepll",
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.ops = &sifive_fu540_prci_tlclksel_clk_ops,
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},
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};
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static const struct prci_clk_desc prci_clk_fu540 = {
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.clks = __prci_init_clocks_fu540,
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.num_clks = ARRAY_SIZE(__prci_init_clocks_fu540),
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};
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#endif /* __SIFIVE_CLK_FU540_PRCI_H */
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@ -1,133 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020-2022 SiFive, Inc.
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* Copyright (C) 2020-2022 Zong Li
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*/
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#include <linux/module.h>
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#include <dt-bindings/clock/sifive-fu740-prci.h>
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#include "sifive-prci.h"
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/* PRCI integration data for each WRPLL instance */
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static struct __prci_wrpll_data sifive_fu740_prci_corepll_data = {
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.cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
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.cfg1_offs = PRCI_COREPLLCFG1_OFFSET,
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.enable_bypass = sifive_prci_coreclksel_use_hfclk,
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.disable_bypass = sifive_prci_coreclksel_use_final_corepll,
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};
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static struct __prci_wrpll_data sifive_fu740_prci_ddrpll_data = {
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.cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
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.cfg1_offs = PRCI_DDRPLLCFG1_OFFSET,
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};
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static struct __prci_wrpll_data sifive_fu740_prci_gemgxlpll_data = {
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.cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
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.cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET,
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};
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static struct __prci_wrpll_data sifive_fu740_prci_dvfscorepll_data = {
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.cfg0_offs = PRCI_DVFSCOREPLLCFG0_OFFSET,
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.cfg1_offs = PRCI_DVFSCOREPLLCFG1_OFFSET,
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.enable_bypass = sifive_prci_corepllsel_use_corepll,
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.disable_bypass = sifive_prci_corepllsel_use_dvfscorepll,
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};
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static struct __prci_wrpll_data sifive_fu740_prci_hfpclkpll_data = {
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.cfg0_offs = PRCI_HFPCLKPLLCFG0_OFFSET,
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.cfg1_offs = PRCI_HFPCLKPLLCFG1_OFFSET,
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.enable_bypass = sifive_prci_hfpclkpllsel_use_hfclk,
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.disable_bypass = sifive_prci_hfpclkpllsel_use_hfpclkpll,
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};
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static struct __prci_wrpll_data sifive_fu740_prci_cltxpll_data = {
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.cfg0_offs = PRCI_CLTXPLLCFG0_OFFSET,
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.cfg1_offs = PRCI_CLTXPLLCFG1_OFFSET,
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};
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/* Linux clock framework integration */
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static const struct clk_ops sifive_fu740_prci_wrpll_clk_ops = {
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.set_rate = sifive_prci_wrpll_set_rate,
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.round_rate = sifive_prci_wrpll_round_rate,
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.recalc_rate = sifive_prci_wrpll_recalc_rate,
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.enable = sifive_prci_clock_enable,
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.disable = sifive_prci_clock_disable,
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.is_enabled = sifive_clk_is_enabled,
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};
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static const struct clk_ops sifive_fu740_prci_wrpll_ro_clk_ops = {
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.recalc_rate = sifive_prci_wrpll_recalc_rate,
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};
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static const struct clk_ops sifive_fu740_prci_tlclksel_clk_ops = {
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.recalc_rate = sifive_prci_tlclksel_recalc_rate,
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};
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static const struct clk_ops sifive_fu740_prci_hfpclkplldiv_clk_ops = {
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.recalc_rate = sifive_prci_hfpclkplldiv_recalc_rate,
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};
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static const struct clk_ops sifive_fu740_prci_pcie_aux_clk_ops = {
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.enable = sifive_prci_pcie_aux_clock_enable,
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.disable = sifive_prci_pcie_aux_clock_disable,
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.is_enabled = sifive_prci_pcie_aux_clock_is_enabled,
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};
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/* List of clock controls provided by the PRCI */
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struct __prci_clock __prci_init_clocks_fu740[] = {
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[FU740_PRCI_CLK_COREPLL] = {
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.name = "corepll",
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.parent_name = "hfclk",
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.ops = &sifive_fu740_prci_wrpll_clk_ops,
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.pwd = &sifive_fu740_prci_corepll_data,
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},
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[FU740_PRCI_CLK_DDRPLL] = {
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.name = "ddrpll",
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.parent_name = "hfclk",
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.ops = &sifive_fu740_prci_wrpll_ro_clk_ops,
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.pwd = &sifive_fu740_prci_ddrpll_data,
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},
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[FU740_PRCI_CLK_GEMGXLPLL] = {
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.name = "gemgxlpll",
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.parent_name = "hfclk",
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.ops = &sifive_fu740_prci_wrpll_clk_ops,
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.pwd = &sifive_fu740_prci_gemgxlpll_data,
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},
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[FU740_PRCI_CLK_DVFSCOREPLL] = {
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.name = "dvfscorepll",
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.parent_name = "hfclk",
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.ops = &sifive_fu740_prci_wrpll_clk_ops,
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.pwd = &sifive_fu740_prci_dvfscorepll_data,
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},
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[FU740_PRCI_CLK_HFPCLKPLL] = {
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.name = "hfpclkpll",
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.parent_name = "hfclk",
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.ops = &sifive_fu740_prci_wrpll_clk_ops,
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.pwd = &sifive_fu740_prci_hfpclkpll_data,
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},
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[FU740_PRCI_CLK_CLTXPLL] = {
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.name = "cltxpll",
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.parent_name = "hfclk",
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.ops = &sifive_fu740_prci_wrpll_clk_ops,
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.pwd = &sifive_fu740_prci_cltxpll_data,
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},
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[FU740_PRCI_CLK_TLCLK] = {
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.name = "tlclk",
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.parent_name = "corepll",
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.ops = &sifive_fu740_prci_tlclksel_clk_ops,
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},
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[FU740_PRCI_CLK_PCLK] = {
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.name = "pclk",
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.parent_name = "hfpclkpll",
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.ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops,
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},
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[FU740_PRCI_CLK_PCIE_AUX] = {
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.name = "pcie_aux",
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.parent_name = "hfclk",
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.ops = &sifive_fu740_prci_pcie_aux_clk_ops,
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},
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};
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@ -1,17 +1,139 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 SiFive, Inc.
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* Zong Li
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* Copyright (C) 2020-2021 SiFive, Inc.
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* Copyright (C) 2020-2021 Zong Li
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*/
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#ifndef __SIFIVE_CLK_FU740_PRCI_H
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#define __SIFIVE_CLK_FU740_PRCI_H
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#include <linux/module.h>
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#include <dt-bindings/clock/sifive-fu740-prci.h>
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#include "sifive-prci.h"
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#define NUM_CLOCK_FU740 9
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/* PRCI integration data for each WRPLL instance */
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extern struct __prci_clock __prci_init_clocks_fu740[NUM_CLOCK_FU740];
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static struct __prci_wrpll_data sifive_fu740_prci_corepll_data = {
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.cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
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.cfg1_offs = PRCI_COREPLLCFG1_OFFSET,
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.enable_bypass = sifive_prci_coreclksel_use_hfclk,
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.disable_bypass = sifive_prci_coreclksel_use_final_corepll,
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};
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static struct __prci_wrpll_data sifive_fu740_prci_ddrpll_data = {
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.cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
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.cfg1_offs = PRCI_DDRPLLCFG1_OFFSET,
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};
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static struct __prci_wrpll_data sifive_fu740_prci_gemgxlpll_data = {
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.cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
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.cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET,
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};
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static struct __prci_wrpll_data sifive_fu740_prci_dvfscorepll_data = {
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.cfg0_offs = PRCI_DVFSCOREPLLCFG0_OFFSET,
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.cfg1_offs = PRCI_DVFSCOREPLLCFG1_OFFSET,
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.enable_bypass = sifive_prci_corepllsel_use_corepll,
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.disable_bypass = sifive_prci_corepllsel_use_dvfscorepll,
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};
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static struct __prci_wrpll_data sifive_fu740_prci_hfpclkpll_data = {
|
||||
.cfg0_offs = PRCI_HFPCLKPLLCFG0_OFFSET,
|
||||
.cfg1_offs = PRCI_HFPCLKPLLCFG1_OFFSET,
|
||||
.enable_bypass = sifive_prci_hfpclkpllsel_use_hfclk,
|
||||
.disable_bypass = sifive_prci_hfpclkpllsel_use_hfpclkpll,
|
||||
};
|
||||
|
||||
static struct __prci_wrpll_data sifive_fu740_prci_cltxpll_data = {
|
||||
.cfg0_offs = PRCI_CLTXPLLCFG0_OFFSET,
|
||||
.cfg1_offs = PRCI_CLTXPLLCFG1_OFFSET,
|
||||
};
|
||||
|
||||
/* Linux clock framework integration */
|
||||
|
||||
static const struct clk_ops sifive_fu740_prci_wrpll_clk_ops = {
|
||||
.set_rate = sifive_prci_wrpll_set_rate,
|
||||
.round_rate = sifive_prci_wrpll_round_rate,
|
||||
.recalc_rate = sifive_prci_wrpll_recalc_rate,
|
||||
.enable = sifive_prci_clock_enable,
|
||||
.disable = sifive_prci_clock_disable,
|
||||
.is_enabled = sifive_clk_is_enabled,
|
||||
};
|
||||
|
||||
static const struct clk_ops sifive_fu740_prci_wrpll_ro_clk_ops = {
|
||||
.recalc_rate = sifive_prci_wrpll_recalc_rate,
|
||||
};
|
||||
|
||||
static const struct clk_ops sifive_fu740_prci_tlclksel_clk_ops = {
|
||||
.recalc_rate = sifive_prci_tlclksel_recalc_rate,
|
||||
};
|
||||
|
||||
static const struct clk_ops sifive_fu740_prci_hfpclkplldiv_clk_ops = {
|
||||
.recalc_rate = sifive_prci_hfpclkplldiv_recalc_rate,
|
||||
};
|
||||
|
||||
static const struct clk_ops sifive_fu740_prci_pcie_aux_clk_ops = {
|
||||
.enable = sifive_prci_pcie_aux_clock_enable,
|
||||
.disable = sifive_prci_pcie_aux_clock_disable,
|
||||
.is_enabled = sifive_prci_pcie_aux_clock_is_enabled,
|
||||
};
|
||||
|
||||
/* List of clock controls provided by the PRCI */
|
||||
static struct __prci_clock __prci_init_clocks_fu740[] = {
|
||||
[FU740_PRCI_CLK_COREPLL] = {
|
||||
.name = "corepll",
|
||||
.parent_name = "hfclk",
|
||||
.ops = &sifive_fu740_prci_wrpll_clk_ops,
|
||||
.pwd = &sifive_fu740_prci_corepll_data,
|
||||
},
|
||||
[FU740_PRCI_CLK_DDRPLL] = {
|
||||
.name = "ddrpll",
|
||||
.parent_name = "hfclk",
|
||||
.ops = &sifive_fu740_prci_wrpll_ro_clk_ops,
|
||||
.pwd = &sifive_fu740_prci_ddrpll_data,
|
||||
},
|
||||
[FU740_PRCI_CLK_GEMGXLPLL] = {
|
||||
.name = "gemgxlpll",
|
||||
.parent_name = "hfclk",
|
||||
.ops = &sifive_fu740_prci_wrpll_clk_ops,
|
||||
.pwd = &sifive_fu740_prci_gemgxlpll_data,
|
||||
},
|
||||
[FU740_PRCI_CLK_DVFSCOREPLL] = {
|
||||
.name = "dvfscorepll",
|
||||
.parent_name = "hfclk",
|
||||
.ops = &sifive_fu740_prci_wrpll_clk_ops,
|
||||
.pwd = &sifive_fu740_prci_dvfscorepll_data,
|
||||
},
|
||||
[FU740_PRCI_CLK_HFPCLKPLL] = {
|
||||
.name = "hfpclkpll",
|
||||
.parent_name = "hfclk",
|
||||
.ops = &sifive_fu740_prci_wrpll_clk_ops,
|
||||
.pwd = &sifive_fu740_prci_hfpclkpll_data,
|
||||
},
|
||||
[FU740_PRCI_CLK_CLTXPLL] = {
|
||||
.name = "cltxpll",
|
||||
.parent_name = "hfclk",
|
||||
.ops = &sifive_fu740_prci_wrpll_clk_ops,
|
||||
.pwd = &sifive_fu740_prci_cltxpll_data,
|
||||
},
|
||||
[FU740_PRCI_CLK_TLCLK] = {
|
||||
.name = "tlclk",
|
||||
.parent_name = "corepll",
|
||||
.ops = &sifive_fu740_prci_tlclksel_clk_ops,
|
||||
},
|
||||
[FU740_PRCI_CLK_PCLK] = {
|
||||
.name = "pclk",
|
||||
.parent_name = "hfpclkpll",
|
||||
.ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops,
|
||||
},
|
||||
[FU740_PRCI_CLK_PCIE_AUX] = {
|
||||
.name = "pcie_aux",
|
||||
.parent_name = "hfclk",
|
||||
.ops = &sifive_fu740_prci_pcie_aux_clk_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct prci_clk_desc prci_clk_fu740 = {
|
||||
.clks = __prci_init_clocks_fu740,
|
||||
|
||||
@ -12,11 +12,6 @@
|
||||
#include "fu540-prci.h"
|
||||
#include "fu740-prci.h"
|
||||
|
||||
static const struct prci_clk_desc prci_clk_fu540 = {
|
||||
.clks = __prci_init_clocks_fu540,
|
||||
.num_clks = ARRAY_SIZE(__prci_init_clocks_fu540),
|
||||
};
|
||||
|
||||
/*
|
||||
* Private functions
|
||||
*/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user