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microblaze: Define correct L1_CACHE_SHIFT value

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Microblaze cacheline length is configurable and current cpu
uses two cacheline length 4 and 8.

We are taking conservative maximum value to be sure that cacheline
alignment is satisfied for all cases.

Here is the calculation for cacheline lenght 8  32bit=4Byte values
which is corresponding with SHIFT 5.

Signed-off-by: Michal Simek <monstr@monstr.eu>
This commit is contained in:
Michal Simek 2010-04-26 13:43:23 +02:00
parent 77543cebab
commit 598acab44d
1 changed files with 1 additions and 1 deletions
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2
arch/microblaze/include/asm/cache.h
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@ -15,7 +15,7 @@
#include <asm/registers.h>
#define L1_CACHE_SHIFT 2
#define L1_CACHE_SHIFT 5
/* word-granular cache in microblaze */
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)