Merge branch 'macb-fixes'
Andy Shevchenko says: ==================== net/macb: fix for AVR32 and clean up It seems no one had tested recently the driver on AVR32 platforms such as ATNGW100. This series bring it back to work. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
54109da31f
@ -104,6 +104,57 @@ static void *macb_rx_buffer(struct macb *bp, unsigned int index)
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return bp->rx_buffers + bp->rx_buffer_size * macb_rx_ring_wrap(index);
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}
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/* I/O accessors */
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static u32 hw_readl_native(struct macb *bp, int offset)
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{
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return __raw_readl(bp->regs + offset);
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}
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static void hw_writel_native(struct macb *bp, int offset, u32 value)
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{
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__raw_writel(value, bp->regs + offset);
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}
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static u32 hw_readl(struct macb *bp, int offset)
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{
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return readl_relaxed(bp->regs + offset);
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}
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static void hw_writel(struct macb *bp, int offset, u32 value)
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{
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writel_relaxed(value, bp->regs + offset);
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}
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/*
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* Find the CPU endianness by using the loopback bit of NCR register. When the
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* CPU is in big endian we need to program swaped mode for management
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* descriptor access.
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*/
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static bool hw_is_native_io(void __iomem *addr)
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{
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u32 value = MACB_BIT(LLB);
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__raw_writel(value, addr + MACB_NCR);
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value = __raw_readl(addr + MACB_NCR);
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/* Write 0 back to disable everything */
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__raw_writel(0, addr + MACB_NCR);
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return value == MACB_BIT(LLB);
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}
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static bool hw_is_gem(void __iomem *addr, bool native_io)
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{
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u32 id;
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if (native_io)
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id = __raw_readl(addr + MACB_MID);
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else
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id = readl_relaxed(addr + MACB_MID);
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return MACB_BFEXT(IDNUM, id) >= 0x2;
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}
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static void macb_set_hwaddr(struct macb *bp)
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{
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u32 bottom;
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@ -160,7 +211,7 @@ static void macb_get_hwaddr(struct macb *bp)
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}
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}
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netdev_info(bp->dev, "invalid hw address, using random\n");
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dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
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eth_hw_addr_random(bp->dev);
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}
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@ -252,7 +303,6 @@ static void macb_handle_link_change(struct net_device *dev)
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struct macb *bp = netdev_priv(dev);
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struct phy_device *phydev = bp->phy_dev;
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unsigned long flags;
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int status_change = 0;
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spin_lock_irqsave(&bp->lock, flags);
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@ -449,14 +499,14 @@ err_out:
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static void macb_update_stats(struct macb *bp)
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{
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u32 __iomem *reg = bp->regs + MACB_PFR;
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u32 *p = &bp->hw_stats.macb.rx_pause_frames;
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u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
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int offset = MACB_PFR;
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WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
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for(; p < end; p++, reg++)
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*p += readl_relaxed(reg);
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for(; p < end; p++, offset += 4)
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*p += bp->readl(bp, offset);
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}
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static int macb_halt_tx(struct macb *bp)
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@ -1107,12 +1157,6 @@ static void macb_poll_controller(struct net_device *dev)
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}
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#endif
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static inline unsigned int macb_count_tx_descriptors(struct macb *bp,
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unsigned int len)
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{
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return (len + bp->max_tx_length - 1) / bp->max_tx_length;
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}
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static unsigned int macb_tx_map(struct macb *bp,
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struct macb_queue *queue,
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struct sk_buff *skb)
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@ -1263,11 +1307,11 @@ static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
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* socket buffer: skb fragments of jumbo frames may need to be
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* splitted into many buffer descriptors.
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*/
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count = macb_count_tx_descriptors(bp, skb_headlen(skb));
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count = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length);
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nr_frags = skb_shinfo(skb)->nr_frags;
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for (f = 0; f < nr_frags; f++) {
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frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
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count += macb_count_tx_descriptors(bp, frag_size);
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count += DIV_ROUND_UP(frag_size, bp->max_tx_length);
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}
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spin_lock_irqsave(&bp->lock, flags);
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@ -1603,7 +1647,6 @@ static u32 macb_dbw(struct macb *bp)
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static void macb_configure_dma(struct macb *bp)
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{
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u32 dmacfg;
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u32 tmp, ncr;
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if (macb_is_gem(bp)) {
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dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
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@ -1613,22 +1656,11 @@ static void macb_configure_dma(struct macb *bp)
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dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
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dmacfg &= ~GEM_BIT(ENDIA_PKT);
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/* Find the CPU endianness by using the loopback bit of net_ctrl
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* register. save it first. When the CPU is in big endian we
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* need to program swaped mode for management descriptor access.
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*/
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ncr = macb_readl(bp, NCR);
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__raw_writel(MACB_BIT(LLB), bp->regs + MACB_NCR);
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tmp = __raw_readl(bp->regs + MACB_NCR);
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if (tmp == MACB_BIT(LLB))
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if (bp->native_io)
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dmacfg &= ~GEM_BIT(ENDIA_DESC);
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else
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dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
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/* Restore net_ctrl */
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macb_writel(bp, NCR, ncr);
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if (bp->dev->features & NETIF_F_HW_CSUM)
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dmacfg |= GEM_BIT(TXCOEN);
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else
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@ -1897,19 +1929,19 @@ static int macb_change_mtu(struct net_device *dev, int new_mtu)
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static void gem_update_stats(struct macb *bp)
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{
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int i;
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unsigned int i;
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u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
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for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
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u32 offset = gem_statistics[i].offset;
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u64 val = readl_relaxed(bp->regs + offset);
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u64 val = bp->readl(bp, offset);
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bp->ethtool_stats[i] += val;
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*p += val;
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if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
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/* Add GEM_OCTTXH, GEM_OCTRXH */
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val = readl_relaxed(bp->regs + offset + 4);
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val = bp->readl(bp, offset + 4);
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bp->ethtool_stats[i] += ((u64)val) << 32;
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*(++p) += val;
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}
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@ -1976,7 +2008,7 @@ static int gem_get_sset_count(struct net_device *dev, int sset)
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static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
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{
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int i;
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unsigned int i;
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switch (sset) {
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case ETH_SS_STATS:
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@ -2190,7 +2222,7 @@ static void macb_configure_caps(struct macb *bp, const struct macb_config *dt_co
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if (dt_conf)
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bp->caps = dt_conf->caps;
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if (macb_is_gem_hw(bp->regs)) {
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if (hw_is_gem(bp->regs, bp->native_io)) {
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bp->caps |= MACB_CAPS_MACB_IS_GEM;
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dcfg = gem_readl(bp, DCFG1);
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@ -2201,10 +2233,11 @@ static void macb_configure_caps(struct macb *bp, const struct macb_config *dt_co
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bp->caps |= MACB_CAPS_FIFO_MODE;
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}
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netdev_dbg(bp->dev, "Cadence caps 0x%08x\n", bp->caps);
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dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps);
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}
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static void macb_probe_queues(void __iomem *mem,
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bool native_io,
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unsigned int *queue_mask,
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unsigned int *num_queues)
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{
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@ -2219,7 +2252,7 @@ static void macb_probe_queues(void __iomem *mem,
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* we are early in the probe process and don't have the
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* MACB_CAPS_MACB_IS_GEM flag positioned
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*/
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if (!macb_is_gem_hw(mem))
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if (!hw_is_gem(mem, native_io))
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return;
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/* bit 0 is never set but queue 0 always exists */
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@ -2786,6 +2819,7 @@ static int macb_probe(struct platform_device *pdev)
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struct clk *pclk, *hclk, *tx_clk;
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unsigned int queue_mask, num_queues;
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struct macb_platform_data *pdata;
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bool native_io;
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struct phy_device *phydev;
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struct net_device *dev;
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struct resource *regs;
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@ -2794,6 +2828,11 @@ static int macb_probe(struct platform_device *pdev)
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struct macb *bp;
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int err;
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regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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mem = devm_ioremap_resource(&pdev->dev, regs);
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if (IS_ERR(mem))
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return PTR_ERR(mem);
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if (np) {
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const struct of_device_id *match;
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@ -2809,14 +2848,9 @@ static int macb_probe(struct platform_device *pdev)
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if (err)
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return err;
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regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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mem = devm_ioremap_resource(&pdev->dev, regs);
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if (IS_ERR(mem)) {
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err = PTR_ERR(mem);
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goto err_disable_clocks;
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}
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native_io = hw_is_native_io(mem);
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macb_probe_queues(mem, &queue_mask, &num_queues);
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macb_probe_queues(mem, native_io, &queue_mask, &num_queues);
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dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
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if (!dev) {
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err = -ENOMEM;
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@ -2831,6 +2865,14 @@ static int macb_probe(struct platform_device *pdev)
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bp->pdev = pdev;
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bp->dev = dev;
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bp->regs = mem;
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bp->native_io = native_io;
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if (native_io) {
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bp->readl = hw_readl_native;
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bp->writel = hw_writel_native;
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} else {
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bp->readl = hw_readl;
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bp->writel = hw_writel;
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}
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bp->num_queues = num_queues;
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bp->queue_mask = queue_mask;
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if (macb_config)
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@ -2838,9 +2880,8 @@ static int macb_probe(struct platform_device *pdev)
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bp->pclk = pclk;
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bp->hclk = hclk;
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bp->tx_clk = tx_clk;
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if (macb_config->jumbo_max_len) {
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if (macb_config)
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bp->jumbo_max_len = macb_config->jumbo_max_len;
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}
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spin_lock_init(&bp->lock);
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@ -429,18 +429,12 @@
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| GEM_BF(name, value))
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/* Register access macros */
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#define macb_readl(port,reg) \
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readl_relaxed((port)->regs + MACB_##reg)
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#define macb_writel(port,reg,value) \
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writel_relaxed((value), (port)->regs + MACB_##reg)
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#define gem_readl(port, reg) \
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readl_relaxed((port)->regs + GEM_##reg)
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#define gem_writel(port, reg, value) \
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writel_relaxed((value), (port)->regs + GEM_##reg)
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#define queue_readl(queue, reg) \
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readl_relaxed((queue)->bp->regs + (queue)->reg)
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#define queue_writel(queue, reg, value) \
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writel_relaxed((value), (queue)->bp->regs + (queue)->reg)
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#define macb_readl(port, reg) (port)->readl((port), MACB_##reg)
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#define macb_writel(port, reg, value) (port)->writel((port), MACB_##reg, (value))
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#define gem_readl(port, reg) (port)->readl((port), GEM_##reg)
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#define gem_writel(port, reg, value) (port)->writel((port), GEM_##reg, (value))
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#define queue_readl(queue, reg) (queue)->bp->readl((queue)->bp, (queue)->reg)
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#define queue_writel(queue, reg, value) (queue)->bp->writel((queue)->bp, (queue)->reg, (value))
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/* Conditional GEM/MACB macros. These perform the operation to the correct
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* register dependent on whether the device is a GEM or a MACB. For registers
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@ -785,6 +779,11 @@ struct macb_queue {
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struct macb {
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void __iomem *regs;
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bool native_io;
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/* hardware IO accessors */
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u32 (*readl)(struct macb *bp, int offset);
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void (*writel)(struct macb *bp, int offset, u32 value);
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unsigned int rx_tail;
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unsigned int rx_prepared_head;
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@ -817,9 +816,9 @@ struct macb {
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struct mii_bus *mii_bus;
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struct phy_device *phy_dev;
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unsigned int link;
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unsigned int speed;
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unsigned int duplex;
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int link;
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int speed;
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int duplex;
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u32 caps;
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unsigned int dma_burst_length;
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@ -843,9 +842,4 @@ static inline bool macb_is_gem(struct macb *bp)
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return !!(bp->caps & MACB_CAPS_MACB_IS_GEM);
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}
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static inline bool macb_is_gem_hw(void __iomem *addr)
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{
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return !!(MACB_BFEXT(IDNUM, readl_relaxed(addr + MACB_MID)) >= 0x2);
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}
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#endif /* _MACB_H */
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@ -8,11 +8,19 @@
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#ifndef __MACB_PDATA_H__
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#define __MACB_PDATA_H__
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/**
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* struct macb_platform_data - platform data for MACB Ethernet
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* @phy_mask: phy mask passed when register the MDIO bus
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* within the driver
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* @phy_irq_pin: PHY IRQ
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* @is_rmii: using RMII interface?
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* @rev_eth_addr: reverse Ethernet address byte order
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*/
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struct macb_platform_data {
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u32 phy_mask;
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int phy_irq_pin; /* PHY IRQ */
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u8 is_rmii; /* using RMII interface? */
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u8 rev_eth_addr; /* reverse Ethernet address byte order */
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int phy_irq_pin;
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u8 is_rmii;
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u8 rev_eth_addr;
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};
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#endif /* __MACB_PDATA_H__ */
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