forked from Minki/linux
crypto: qat - add AES-XTS support for QAT GEN4 devices
Add handling of AES-XTS specific to QAT GEN4 devices. Co-developed-by: Tomaszx Kowalik <tomaszx.kowalik@intel.com> Signed-off-by: Tomaszx Kowalik <tomaszx.kowalik@intel.com> Signed-off-by: Marco Chiappero <marco.chiappero@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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@ -33,6 +33,11 @@
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ICP_QAT_HW_CIPHER_KEY_CONVERT, \
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ICP_QAT_HW_CIPHER_DECRYPT)
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#define QAT_AES_HW_CONFIG_DEC_NO_CONV(alg, mode) \
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ICP_QAT_HW_CIPHER_CONFIG_BUILD(mode, alg, \
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ICP_QAT_HW_CIPHER_NO_CONVERT, \
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ICP_QAT_HW_CIPHER_DECRYPT)
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#define HW_CAP_AES_V2(accel_dev) \
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(GET_HW_DATA(accel_dev)->accel_capabilities_mask & \
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ICP_ACCEL_CAPABILITIES_AES_V2)
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@ -95,6 +100,7 @@ struct qat_alg_skcipher_ctx {
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struct icp_qat_fw_la_bulk_req dec_fw_req;
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struct qat_crypto_instance *inst;
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struct crypto_skcipher *ftfm;
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struct crypto_cipher *tweak;
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bool fallback;
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int mode;
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};
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@ -428,7 +434,16 @@ static void qat_alg_skcipher_init_com(struct qat_alg_skcipher_ctx *ctx,
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cd_pars->u.s.content_desc_params_sz =
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sizeof(struct icp_qat_hw_cipher_algo_blk) >> 3;
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if (aes_v2_capable && mode == ICP_QAT_HW_CIPHER_CTR_MODE) {
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if (aes_v2_capable && mode == ICP_QAT_HW_CIPHER_XTS_MODE) {
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ICP_QAT_FW_LA_SLICE_TYPE_SET(header->serv_specif_flags,
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ICP_QAT_FW_LA_USE_UCS_SLICE_TYPE);
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/* Store both XTS keys in CD, only the first key is sent
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* to the HW, the second key is used for tweak calculation
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*/
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memcpy(cd->ucs_aes.key, key, keylen);
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keylen = keylen / 2;
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} else if (aes_v2_capable && mode == ICP_QAT_HW_CIPHER_CTR_MODE) {
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ICP_QAT_FW_LA_SLICE_TYPE_SET(header->serv_specif_flags,
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ICP_QAT_FW_LA_USE_UCS_SLICE_TYPE);
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keylen = round_up(keylen, 16);
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@ -458,6 +473,28 @@ static void qat_alg_skcipher_init_enc(struct qat_alg_skcipher_ctx *ctx,
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enc_cd->aes.cipher_config.val = QAT_AES_HW_CONFIG_ENC(alg, mode);
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}
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static void qat_alg_xts_reverse_key(const u8 *key_forward, unsigned int keylen,
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u8 *key_reverse)
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{
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struct crypto_aes_ctx aes_expanded;
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int nrounds;
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u8 *key;
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aes_expandkey(&aes_expanded, key_forward, keylen);
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if (keylen == AES_KEYSIZE_128) {
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nrounds = 10;
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key = (u8 *)aes_expanded.key_enc + (AES_BLOCK_SIZE * nrounds);
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memcpy(key_reverse, key, AES_BLOCK_SIZE);
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} else {
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/* AES_KEYSIZE_256 */
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nrounds = 14;
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key = (u8 *)aes_expanded.key_enc + (AES_BLOCK_SIZE * nrounds);
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memcpy(key_reverse, key, AES_BLOCK_SIZE);
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memcpy(key_reverse + AES_BLOCK_SIZE, key - AES_BLOCK_SIZE,
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AES_BLOCK_SIZE);
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}
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}
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static void qat_alg_skcipher_init_dec(struct qat_alg_skcipher_ctx *ctx,
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int alg, const u8 *key,
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unsigned int keylen, int mode)
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@ -465,16 +502,26 @@ static void qat_alg_skcipher_init_dec(struct qat_alg_skcipher_ctx *ctx,
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struct icp_qat_hw_cipher_algo_blk *dec_cd = ctx->dec_cd;
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struct icp_qat_fw_la_bulk_req *req = &ctx->dec_fw_req;
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struct icp_qat_fw_comn_req_hdr_cd_pars *cd_pars = &req->cd_pars;
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bool aes_v2_capable = HW_CAP_AES_V2(ctx->inst->accel_dev);
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qat_alg_skcipher_init_com(ctx, req, dec_cd, key, keylen);
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cd_pars->u.s.content_desc_addr = ctx->dec_cd_paddr;
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if (mode != ICP_QAT_HW_CIPHER_CTR_MODE)
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if (aes_v2_capable && mode == ICP_QAT_HW_CIPHER_XTS_MODE) {
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/* Key reversing not supported, set no convert */
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dec_cd->aes.cipher_config.val =
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QAT_AES_HW_CONFIG_DEC_NO_CONV(alg, mode);
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/* In-place key reversal */
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qat_alg_xts_reverse_key(dec_cd->ucs_aes.key, keylen / 2,
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dec_cd->ucs_aes.key);
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} else if (mode != ICP_QAT_HW_CIPHER_CTR_MODE) {
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dec_cd->aes.cipher_config.val =
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QAT_AES_HW_CONFIG_DEC(alg, mode);
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else
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} else {
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dec_cd->aes.cipher_config.val =
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QAT_AES_HW_CONFIG_ENC(alg, mode);
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}
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}
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static int qat_alg_validate_key(int key_len, int *alg, int mode)
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@ -1081,8 +1128,33 @@ static int qat_alg_skcipher_xts_setkey(struct crypto_skcipher *tfm,
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ctx->fallback = false;
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return qat_alg_skcipher_setkey(tfm, key, keylen,
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ICP_QAT_HW_CIPHER_XTS_MODE);
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ret = qat_alg_skcipher_setkey(tfm, key, keylen,
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ICP_QAT_HW_CIPHER_XTS_MODE);
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if (ret)
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return ret;
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if (HW_CAP_AES_V2(ctx->inst->accel_dev))
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ret = crypto_cipher_setkey(ctx->tweak, key + (keylen / 2),
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keylen / 2);
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return ret;
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}
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static void qat_alg_set_req_iv(struct qat_crypto_request *qat_req)
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{
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struct icp_qat_fw_la_cipher_req_params *cipher_param;
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struct qat_alg_skcipher_ctx *ctx = qat_req->skcipher_ctx;
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bool aes_v2_capable = HW_CAP_AES_V2(ctx->inst->accel_dev);
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u8 *iv = qat_req->skcipher_req->iv;
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cipher_param = (void *)&qat_req->req.serv_specif_rqpars;
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if (aes_v2_capable && ctx->mode == ICP_QAT_HW_CIPHER_XTS_MODE)
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crypto_cipher_encrypt_one(ctx->tweak,
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(u8 *)cipher_param->u.cipher_IV_array,
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iv);
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else
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memcpy(cipher_param->u.cipher_IV_array, iv, AES_BLOCK_SIZE);
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}
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static int qat_alg_skcipher_encrypt(struct skcipher_request *req)
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@ -1114,7 +1186,8 @@ static int qat_alg_skcipher_encrypt(struct skcipher_request *req)
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cipher_param = (void *)&qat_req->req.serv_specif_rqpars;
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cipher_param->cipher_length = req->cryptlen;
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cipher_param->cipher_offset = 0;
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memcpy(cipher_param->u.cipher_IV_array, req->iv, AES_BLOCK_SIZE);
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qat_alg_set_req_iv(qat_req);
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do {
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ret = adf_send_message(ctx->inst->sym_tx, (u32 *)msg);
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@ -1182,8 +1255,8 @@ static int qat_alg_skcipher_decrypt(struct skcipher_request *req)
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cipher_param = (void *)&qat_req->req.serv_specif_rqpars;
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cipher_param->cipher_length = req->cryptlen;
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cipher_param->cipher_offset = 0;
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memcpy(cipher_param->u.cipher_IV_array, req->iv, AES_BLOCK_SIZE);
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qat_alg_set_req_iv(qat_req);
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qat_alg_update_iv(qat_req);
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do {
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@ -1293,6 +1366,12 @@ static int qat_alg_skcipher_init_xts_tfm(struct crypto_skcipher *tfm)
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if (IS_ERR(ctx->ftfm))
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return PTR_ERR(ctx->ftfm);
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ctx->tweak = crypto_alloc_cipher("aes", 0, 0);
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if (IS_ERR(ctx->tweak)) {
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crypto_free_skcipher(ctx->ftfm);
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return PTR_ERR(ctx->tweak);
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}
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reqsize = max(sizeof(struct qat_crypto_request),
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sizeof(struct skcipher_request) +
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crypto_skcipher_reqsize(ctx->ftfm));
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@ -1335,6 +1414,9 @@ static void qat_alg_skcipher_exit_xts_tfm(struct crypto_skcipher *tfm)
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if (ctx->ftfm)
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crypto_free_skcipher(ctx->ftfm);
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if (ctx->tweak)
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crypto_free_cipher(ctx->tweak);
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qat_alg_skcipher_exit_tfm(tfm);
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}
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