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crypto: qat - add AES-CTR support for QAT GEN4 devices

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Add support for AES-CTR for QAT GEN4 devices.
Also, introduce the capability ICP_ACCEL_CAPABILITIES_AES_V2 and the
helper macro HW_CAP_AES_V2, which allow to distinguish between
different HW generations.

Co-developed-by: Tomasz Kowalik <tomaszx.kowalik@intel.com>
Signed-off-by: Tomasz Kowalik <tomaszx.kowalik@intel.com>
Co-developed-by: Mateusz Polrola <mateuszx.potrola@intel.com>
Signed-off-by: Mateusz Polrola <mateuszx.potrola@intel.com>
Signed-off-by: Marco Chiappero <marco.chiappero@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Marco Chiappero 2020-12-01 14:24:49 +00:00 committed by Herbert Xu
parent d33a23b053
commit 67916c9516
3 changed files with 39 additions and 2 deletions
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7
drivers/crypto/qat/qat_common/icp_qat_fw_la.h
View File

@ -33,6 +33,9 @@ struct icp_qat_fw_la_bulk_req {
struct icp_qat_fw_comn_req_cd_ctrl cd_ctrl;
};
#define ICP_QAT_FW_LA_USE_UCS_SLICE_TYPE 1
#define QAT_LA_SLICE_TYPE_BITPOS 14
#define QAT_LA_SLICE_TYPE_MASK 0x3
#define ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS 1
#define ICP_QAT_FW_LA_GCM_IV_LEN_NOT_12_OCTETS 0
#define QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS 12
@ -179,6 +182,10 @@ struct icp_qat_fw_la_bulk_req {
QAT_FIELD_SET(flags, val, QAT_LA_PARTIAL_BITPOS, \
QAT_LA_PARTIAL_MASK)
#define ICP_QAT_FW_LA_SLICE_TYPE_SET(flags, val) \
QAT_FIELD_SET(flags, val, QAT_LA_SLICE_TYPE_BITPOS, \
QAT_LA_SLICE_TYPE_MASK)
struct icp_qat_fw_cipher_req_hdr_cd_pars {
union {
struct {

17
drivers/crypto/qat/qat_common/icp_qat_hw.h
View File

@ -65,6 +65,11 @@ struct icp_qat_hw_auth_config {
__u32 reserved;
};
struct icp_qat_hw_ucs_cipher_config {
__u32 val;
__u32 reserved[3];
};
enum icp_qat_slice_mask {
ICP_ACCEL_MASK_CIPHER_SLICE = BIT(0),
ICP_ACCEL_MASK_AUTH_SLICE = BIT(1),
@ -86,6 +91,8 @@ enum icp_qat_capabilities_mask {
ICP_ACCEL_CAPABILITIES_RAND = BIT(7),
ICP_ACCEL_CAPABILITIES_ZUC = BIT(8),
ICP_ACCEL_CAPABILITIES_SHA3 = BIT(9),
/* Bits 10-25 are currently reserved */
ICP_ACCEL_CAPABILITIES_AES_V2 = BIT(26)
};
#define QAT_AUTH_MODE_BITPOS 4
@ -278,7 +285,15 @@ struct icp_qat_hw_cipher_aes256_f8 {
__u8 key[ICP_QAT_HW_AES_256_F8_KEY_SZ];
};
struct icp_qat_hw_ucs_cipher_aes256_f8 {
struct icp_qat_hw_ucs_cipher_config cipher_config;
__u8 key[ICP_QAT_HW_AES_256_F8_KEY_SZ];
};
struct icp_qat_hw_cipher_algo_blk {
struct icp_qat_hw_cipher_aes256_f8 aes;
union {
struct icp_qat_hw_cipher_aes256_f8 aes;
struct icp_qat_hw_ucs_cipher_aes256_f8 ucs_aes;
};
} __aligned(64);
#endif

17
drivers/crypto/qat/qat_common/qat_algs.c
View File

@ -33,6 +33,10 @@
ICP_QAT_HW_CIPHER_KEY_CONVERT, \
ICP_QAT_HW_CIPHER_DECRYPT)
#define HW_CAP_AES_V2(accel_dev) \
(GET_HW_DATA(accel_dev)->accel_capabilities_mask & \
ICP_ACCEL_CAPABILITIES_AES_V2)
static DEFINE_MUTEX(algs_lock);
static unsigned int active_devs;
@ -416,12 +420,23 @@ static void qat_alg_skcipher_init_com(struct qat_alg_skcipher_ctx *ctx,
struct icp_qat_fw_comn_req_hdr_cd_pars *cd_pars = &req->cd_pars;
struct icp_qat_fw_comn_req_hdr *header = &req->comn_hdr;
struct icp_qat_fw_cipher_cd_ctrl_hdr *cd_ctrl = (void *)&req->cd_ctrl;
bool aes_v2_capable = HW_CAP_AES_V2(ctx->inst->accel_dev);
int mode = ctx->mode;
memcpy(cd->aes.key, key, keylen);
qat_alg_init_common_hdr(header);
header->service_cmd_id = ICP_QAT_FW_LA_CMD_CIPHER;
cd_pars->u.s.content_desc_params_sz =
sizeof(struct icp_qat_hw_cipher_algo_blk) >> 3;
if (aes_v2_capable && mode == ICP_QAT_HW_CIPHER_CTR_MODE) {
ICP_QAT_FW_LA_SLICE_TYPE_SET(header->serv_specif_flags,
ICP_QAT_FW_LA_USE_UCS_SLICE_TYPE);
keylen = round_up(keylen, 16);
memcpy(cd->ucs_aes.key, key, keylen);
} else {
memcpy(cd->aes.key, key, keylen);
}
/* Cipher CD config setup */
cd_ctrl->cipher_key_sz = keylen >> 3;
cd_ctrl->cipher_state_sz = AES_BLOCK_SIZE >> 3;