powerpc/mpic: Remove MPIC_BROKEN_FRR_NIRQS and duplicate irq_count
The mpic->irq_count variable is only used as a software error-checking limit to determine whether or not an IRQ number is valid. In board code which does not manually specify an IRQ count to mpic_alloc(), i.e. 0, it is automatically detected from the number of ISUs and the ISU size. In practice, all hardware ends up with irq_count == num_sources, so all of the runtime checks on mpic->irq_count should just check the value of mpic->num_sources instead. When platform hardware does not correctly report the number of IRQs, which only happens on the MPC85xx/MPC86xx, the MPIC_BROKEN_FRR_NIRQS flag is used to override the detected value of num_sources with the manual irq_count parameter. Since there's no need to manually specify the number of IRQs except in this case, the extra flag can be eliminated and the test changed to "irq_count != 0". Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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				| @ -273,7 +273,6 @@ struct mpic | ||||
| 	unsigned int		isu_size; | ||||
| 	unsigned int		isu_shift; | ||||
| 	unsigned int		isu_mask; | ||||
| 	unsigned int		irq_count; | ||||
| 	/* Number of sources */ | ||||
| 	unsigned int		num_sources; | ||||
| 	/* default senses array */ | ||||
| @ -363,8 +362,6 @@ struct mpic | ||||
| #define MPIC_ENABLE_MCK			0x00000200 | ||||
| /* Disable bias among target selection, spread interrupts evenly */ | ||||
| #define MPIC_NO_BIAS			0x00000400 | ||||
| /* Ignore NIRQS as reported by FRR */ | ||||
| #define MPIC_BROKEN_FRR_NIRQS		0x00000800 | ||||
| /* Destination only supports a single CPU at a time */ | ||||
| #define MPIC_SINGLE_DEST_CPU		0x00001000 | ||||
| /* Enable CoreInt delivery of interrupts */ | ||||
|  | ||||
| @ -36,8 +36,7 @@ | ||||
| void __init corenet_ds_pic_init(void) | ||||
| { | ||||
| 	struct mpic *mpic; | ||||
| 	unsigned int flags = MPIC_BIG_ENDIAN | | ||||
| 				MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU; | ||||
| 	unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU; | ||||
| 
 | ||||
| 	if (ppc_md.get_irq == mpic_get_coreint_irq) | ||||
| 		flags |= MPIC_ENABLE_COREINT; | ||||
|  | ||||
| @ -38,7 +38,7 @@ void __init mpc8536_ds_pic_init(void) | ||||
| { | ||||
| 	struct mpic *mpic = mpic_alloc(NULL, 0, | ||||
| 			  MPIC_WANTS_RESET | | ||||
| 			  MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS, | ||||
| 			  MPIC_BIG_ENDIAN, | ||||
| 			0, 256, " OpenPIC  "); | ||||
| 	BUG_ON(mpic == NULL); | ||||
| 	mpic_init(mpic); | ||||
|  | ||||
| @ -72,13 +72,13 @@ void __init mpc85xx_ds_pic_init(void) | ||||
| 
 | ||||
| 	if (of_flat_dt_is_compatible(root, "fsl,MPC8572DS-CAMP")) { | ||||
| 		mpic = mpic_alloc(NULL, 0, | ||||
| 			MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS | | ||||
| 			MPIC_BIG_ENDIAN | | ||||
| 			MPIC_SINGLE_DEST_CPU, | ||||
| 			0, 256, " OpenPIC  "); | ||||
| 	} else { | ||||
| 		mpic = mpic_alloc(NULL, 0, | ||||
| 			  MPIC_WANTS_RESET | | ||||
| 			  MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS | | ||||
| 			  MPIC_BIG_ENDIAN | | ||||
| 			  MPIC_SINGLE_DEST_CPU, | ||||
| 			0, 256, " OpenPIC  "); | ||||
| 	} | ||||
|  | ||||
| @ -436,7 +436,7 @@ static void __init mpc85xx_mds_pic_init(void) | ||||
| { | ||||
| 	struct mpic *mpic = mpic_alloc(NULL, 0, | ||||
| 			MPIC_WANTS_RESET | MPIC_BIG_ENDIAN | | ||||
| 			MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU, | ||||
| 			MPIC_SINGLE_DEST_CPU, | ||||
| 			0, 256, " OpenPIC  "); | ||||
| 	BUG_ON(mpic == NULL); | ||||
| 
 | ||||
|  | ||||
| @ -49,13 +49,13 @@ void __init mpc85xx_rdb_pic_init(void) | ||||
| 
 | ||||
| 	if (of_flat_dt_is_compatible(root, "fsl,MPC85XXRDB-CAMP")) { | ||||
| 		mpic = mpic_alloc(NULL, 0, | ||||
| 			MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS | | ||||
| 			MPIC_BIG_ENDIAN | | ||||
| 			MPIC_SINGLE_DEST_CPU, | ||||
| 			0, 256, " OpenPIC  "); | ||||
| 	} else { | ||||
| 		mpic = mpic_alloc(NULL, 0, | ||||
| 		  MPIC_WANTS_RESET | | ||||
| 		  MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS | | ||||
| 		  MPIC_BIG_ENDIAN | | ||||
| 		  MPIC_SINGLE_DEST_CPU, | ||||
| 		  0, 256, " OpenPIC  "); | ||||
| 	} | ||||
|  | ||||
| @ -34,7 +34,7 @@ void __init p1010_rdb_pic_init(void) | ||||
| { | ||||
| 	struct mpic *mpic = mpic_alloc(NULL, 0, | ||||
| 	  MPIC_WANTS_RESET | MPIC_BIG_ENDIAN | | ||||
| 	  MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU, | ||||
| 	  MPIC_SINGLE_DEST_CPU, | ||||
| 	  0, 256, " OpenPIC  "); | ||||
| 
 | ||||
| 	BUG_ON(mpic == NULL); | ||||
|  | ||||
| @ -244,7 +244,7 @@ void __init p1022_ds_pic_init(void) | ||||
| { | ||||
| 	struct mpic *mpic = mpic_alloc(NULL, 0, | ||||
| 		MPIC_WANTS_RESET | | ||||
| 		MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS | | ||||
| 		MPIC_BIG_ENDIAN | | ||||
| 		MPIC_SINGLE_DEST_CPU, | ||||
| 		0, 256, " OpenPIC  "); | ||||
| 	BUG_ON(mpic == NULL); | ||||
|  | ||||
| @ -95,7 +95,7 @@ static void __init mpc85xx_rds_pic_init(void) | ||||
| { | ||||
| 	struct mpic *mpic = mpic_alloc(NULL, 0, | ||||
| 		MPIC_WANTS_RESET | MPIC_BIG_ENDIAN | | ||||
| 		MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU, | ||||
| 		MPIC_SINGLE_DEST_CPU, | ||||
| 		0, 256, " OpenPIC  "); | ||||
| 
 | ||||
| 	BUG_ON(mpic == NULL); | ||||
|  | ||||
| @ -45,7 +45,7 @@ void __init xes_mpc85xx_pic_init(void) | ||||
| { | ||||
| 	struct mpic *mpic = mpic_alloc(NULL, 0, | ||||
| 			  MPIC_WANTS_RESET | | ||||
| 			  MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS, | ||||
| 			  MPIC_BIG_ENDIAN, | ||||
| 			0, 256, " OpenPIC  "); | ||||
| 	BUG_ON(mpic == NULL); | ||||
| 	mpic_init(mpic); | ||||
|  | ||||
| @ -39,7 +39,7 @@ void __init mpc86xx_init_irq(void) | ||||
| 
 | ||||
| 	struct mpic *mpic = mpic_alloc(NULL, 0, | ||||
| 			MPIC_WANTS_RESET | MPIC_BIG_ENDIAN | | ||||
| 			MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU, | ||||
| 			MPIC_SINGLE_DEST_CPU, | ||||
| 			0, 256, " MPIC     "); | ||||
| 	BUG_ON(mpic == NULL); | ||||
| 
 | ||||
|  | ||||
| @ -157,8 +157,7 @@ static void __init holly_init_IRQ(void) | ||||
| 	mpic = mpic_alloc(NULL, 0, | ||||
| 			MPIC_BIG_ENDIAN | MPIC_WANTS_RESET | | ||||
| 			MPIC_SPV_EOI | MPIC_NO_PTHROU_DIS | MPIC_REGSET_TSI108, | ||||
| 			24, | ||||
| 			NR_IRQS-4, /* num_sources used */ | ||||
| 			24, 0, | ||||
| 			"Tsi108_PIC"); | ||||
| 
 | ||||
| 	BUG_ON(mpic == NULL); | ||||
|  | ||||
| @ -83,7 +83,7 @@ static void __init linkstation_init_IRQ(void) | ||||
| 	struct mpic *mpic; | ||||
| 
 | ||||
| 	mpic = mpic_alloc(NULL, 0, MPIC_WANTS_RESET, | ||||
| 			4, 32, " EPIC     "); | ||||
| 			4, 0, " EPIC     "); | ||||
| 	BUG_ON(mpic == NULL); | ||||
| 
 | ||||
| 	/* PCI IRQs */ | ||||
|  | ||||
| @ -111,8 +111,7 @@ static void __init mpc7448_hpc2_init_IRQ(void) | ||||
| 	mpic = mpic_alloc(NULL, 0, | ||||
| 			MPIC_BIG_ENDIAN | MPIC_WANTS_RESET | | ||||
| 			MPIC_SPV_EOI | MPIC_NO_PTHROU_DIS | MPIC_REGSET_TSI108, | ||||
| 			24, | ||||
| 			NR_IRQS-4, /* num_sources used */ | ||||
| 			24, 0, | ||||
| 			"Tsi108_PIC"); | ||||
| 
 | ||||
| 	BUG_ON(mpic == NULL); | ||||
|  | ||||
| @ -85,7 +85,7 @@ static void __init storcenter_init_IRQ(void) | ||||
| 	struct mpic *mpic; | ||||
| 
 | ||||
| 	mpic = mpic_alloc(NULL, 0, MPIC_WANTS_RESET, | ||||
| 			16, 32, " OpenPIC  "); | ||||
| 			16, 0, " OpenPIC  "); | ||||
| 	BUG_ON(mpic == NULL); | ||||
| 
 | ||||
| 	/*
 | ||||
|  | ||||
| @ -190,9 +190,7 @@ static void __init pseries_mpic_init_IRQ(void) | ||||
| 	BUG_ON(openpic_addr == 0); | ||||
| 
 | ||||
| 	/* Setup the openpic driver */ | ||||
| 	mpic = mpic_alloc(pSeries_mpic_node, openpic_addr, 0, | ||||
| 			  16, 250, /* isu size, irq count */ | ||||
| 			  " MPIC     "); | ||||
| 	mpic = mpic_alloc(pSeries_mpic_node, openpic_addr, 0, 16, 0, " MPIC     "); | ||||
| 	BUG_ON(mpic == NULL); | ||||
| 
 | ||||
| 	/* Add ISUs */ | ||||
|  | ||||
| @ -873,7 +873,7 @@ int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type) | ||||
| 	DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n", | ||||
| 	    mpic, d->irq, src, flow_type); | ||||
| 
 | ||||
| 	if (src >= mpic->irq_count) | ||||
| 	if (src >= mpic->num_sources) | ||||
| 		return -EINVAL; | ||||
| 
 | ||||
| 	if (flow_type == IRQ_TYPE_NONE) | ||||
| @ -909,7 +909,7 @@ void mpic_set_vector(unsigned int virq, unsigned int vector) | ||||
| 	DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n", | ||||
| 	    mpic, virq, src, vector); | ||||
| 
 | ||||
| 	if (src >= mpic->irq_count) | ||||
| 	if (src >= mpic->num_sources) | ||||
| 		return; | ||||
| 
 | ||||
| 	vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)); | ||||
| @ -926,7 +926,7 @@ void mpic_set_destination(unsigned int virq, unsigned int cpuid) | ||||
| 	DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n", | ||||
| 	    mpic, virq, src, cpuid); | ||||
| 
 | ||||
| 	if (src >= mpic->irq_count) | ||||
| 	if (src >= mpic->num_sources) | ||||
| 		return; | ||||
| 
 | ||||
| 	mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid); | ||||
| @ -1006,7 +1006,7 @@ static int mpic_host_map(struct irq_host *h, unsigned int virq, | ||||
| 		return 0; | ||||
| 	} | ||||
| 
 | ||||
| 	if (hw >= mpic->irq_count) | ||||
| 	if (hw >= mpic->num_sources) | ||||
| 		return -EINVAL; | ||||
| 
 | ||||
| 	mpic_msi_reserve_hwirq(mpic, hw); | ||||
| @ -1221,7 +1221,6 @@ struct mpic * __init mpic_alloc(struct device_node *node, | ||||
| 	mpic->hc_tm.name = name; | ||||
| 
 | ||||
| 	mpic->isu_size = isu_size; | ||||
| 	mpic->irq_count = irq_count; | ||||
| 	mpic->num_sources = 0; /* so far */ | ||||
| 
 | ||||
| 	if (mpic->flags & MPIC_LARGE_VECTORS) | ||||
| @ -1314,8 +1313,8 @@ struct mpic * __init mpic_alloc(struct device_node *node, | ||||
| 	 */ | ||||
| 	greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0)); | ||||
| 	if (isu_size == 0) { | ||||
| 		if (mpic->flags & MPIC_BROKEN_FRR_NIRQS) | ||||
| 			mpic->num_sources = mpic->irq_count; | ||||
| 		if (irq_count) | ||||
| 			mpic->num_sources = irq_count; | ||||
| 		else | ||||
| 			mpic->num_sources = | ||||
| 				((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK) | ||||
| @ -1450,10 +1449,6 @@ void __init mpic_init(struct mpic *mpic) | ||||
| 			       (mpic->ipi_vecs[0] + i)); | ||||
| 	} | ||||
| 
 | ||||
| 	/* Initialize interrupt sources */ | ||||
| 	if (mpic->irq_count == 0) | ||||
| 		mpic->irq_count = mpic->num_sources; | ||||
| 
 | ||||
| 	/* Do the HT PIC fixups on U3 broken mpic */ | ||||
| 	DBG("MPIC flags: %x\n", mpic->flags); | ||||
| 	if ((mpic->flags & MPIC_U3_HT_IRQS) && !(mpic->flags & MPIC_SECONDARY)) { | ||||
|  | ||||
| @ -54,7 +54,7 @@ static int mpic_msi_reserve_u3_hwirqs(struct mpic *mpic) | ||||
| 	for (i = 100; i < 105; i++) | ||||
| 		msi_bitmap_reserve_hwirq(&mpic->msi_bitmap, i); | ||||
| 
 | ||||
| 	for (i = 124; i < mpic->irq_count; i++) | ||||
| 	for (i = 124; i < mpic->num_sources; i++) | ||||
| 		msi_bitmap_reserve_hwirq(&mpic->msi_bitmap, i); | ||||
| 
 | ||||
| 
 | ||||
| @ -83,7 +83,7 @@ int mpic_msi_init_allocator(struct mpic *mpic) | ||||
| { | ||||
| 	int rc; | ||||
| 
 | ||||
| 	rc = msi_bitmap_alloc(&mpic->msi_bitmap, mpic->irq_count, | ||||
| 	rc = msi_bitmap_alloc(&mpic->msi_bitmap, mpic->num_sources, | ||||
| 			      mpic->irqhost->of_node); | ||||
| 	if (rc) | ||||
| 		return rc; | ||||
|  | ||||
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