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tile: remove homegrown L1_CACHE_ALIGN macro

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Let's use the standard L1_CACHE_ALIGN macro instead.

Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp>
Acked-by: Chris Metcalf <cmetcalf@tilera.com>
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FUJITA Tomonori 2010-06-29 16:32:42 +09:00 committed by Chris Metcalf
parent 0707ad30d1
commit 4b2bf4b3fc
1 changed files with 0 additions and 1 deletions
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arch/tile/include/asm/cache.h
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@ -20,7 +20,6 @@
/* bytes per L1 data cache line */
#define L1_CACHE_SHIFT CHIP_L1D_LOG_LINE_SIZE()
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1)) & -L1_CACHE_BYTES)
/* bytes per L1 instruction cache line */
#define L1I_CACHE_SHIFT CHIP_L1I_LOG_LINE_SIZE()