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drm/amdgpu: config HDP_MISC_CNTL.READ_BUFFER_WATERMARK

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To fix applications running across multiple GPU config hang.

Signed-off-by: Xiaogang Chen <xiaogang.chen@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Xiaogang Chen
2022-02-21 16:28:10 -06:00
committed by Alex Deucher
parent 4f0f1b58fb
commit 45f0ff404c
2 changed files with 5 additions and 0 deletions
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3
drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
View File

@@ -146,6 +146,9 @@ static void hdp_v4_0_init_registers(struct amdgpu_device *adev)
WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 4, 0))
WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, READ_BUFFER_WATERMARK, 2);
WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));
WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40));
}

2
drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h
View File

@@ -104,6 +104,7 @@
#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5
#define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x6
#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb
#define HDP_MISC_CNTL__READ_BUFFER_WATERMARK__SHIFT 0xe
#define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15
#define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY__SHIFT 0x17
#define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE__SHIFT 0x18
@@ -118,6 +119,7 @@
#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x00000020L
#define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x00000040L
#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x00000800L
#define HDP_MISC_CNTL__READ_BUFFER_WATERMARK_MASK 0x0000c000L
#define HDP_MISC_CNTL__FED_ENABLE_MASK 0x00200000L
#define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY_MASK 0x00800000L
#define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE_MASK 0x01000000L