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arm64: dts: mediatek: Add infra #reset-cells property for MT8195

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We will use mediatek clock reset as infracfg_ao reset instead of
ti-syscon. To support this, remove property of ti reset and add
property of #reset-cells for mediatek clock reset.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220503093856.22250-17-rex-bc.chen@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Rex-BC Chen
2022-05-03 17:38:56 +08:00
committed by Matthias Brugger
parent a30cc07f9e
commit 4459a59807
1 changed files with 1 additions and 12 deletions
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13
arch/arm64/boot/dts/mediatek/mt8195.dtsi
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@@ -10,7 +10,6 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
#include <dt-bindings/reset/ti-syscon.h>
/ {
compatible = "mediatek,mt8195";
@@ -295,17 +294,7 @@
compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
infracfg_rst: reset-controller {
compatible = "ti,syscon-reset";
#reset-cells = <1>;
ti,reset-bits = <
0x140 18 0x144 18 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* pcie */
0x120 0 0x124 0 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */
0x730 10 0x734 10 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */
0x150 5 0x154 5 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* svs gpu */
>;
};
#reset-cells = <1>;
};
pericfg: syscon@10003000 {