forked from Minki/linux
MIPS: Replace SIBYTE_1956_WAR by CONFIG_SB1_PASS_2_WORKAROUNDS
SB1250 uart bug is related to PASS 2 workarounds. Use config CONFIG_SB1_PASS_2_WORKAROUNDS directly and get rid of SIBYTE_1956_WAR. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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@ -10,7 +10,6 @@
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#define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#define CAVIUM_OCTEON_DCACHE_PREFETCH_WAR \
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OCTEON_IS_MODEL(OCTEON_CN6XXX)
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@ -9,6 +9,5 @@
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#define __ASM_MACH_GENERIC_WAR_H
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#endif /* __ASM_MACH_GENERIC_WAR_H */
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@ -9,6 +9,5 @@
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#define __ASM_MIPS_MACH_IP22_WAR_H
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#endif /* __ASM_MIPS_MACH_IP22_WAR_H */
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@ -9,6 +9,5 @@
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#define __ASM_MIPS_MACH_IP27_WAR_H
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#endif /* __ASM_MIPS_MACH_IP27_WAR_H */
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@ -9,6 +9,5 @@
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#define __ASM_MIPS_MACH_IP28_WAR_H
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#endif /* __ASM_MIPS_MACH_IP28_WAR_H */
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@ -6,6 +6,5 @@
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#define __ASM_MIPS_MACH_IP30_WAR_H
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#endif /* __ASM_MIPS_MACH_IP30_WAR_H */
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@ -9,6 +9,5 @@
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#define __ASM_MIPS_MACH_IP32_WAR_H
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#endif /* __ASM_MIPS_MACH_IP32_WAR_H */
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@ -9,6 +9,5 @@
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#define __ASM_MIPS_MACH_MIPS_WAR_H
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
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@ -9,6 +9,5 @@
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#define __ASM_MIPS_MACH_MIPS_WAR_H
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
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@ -9,6 +9,5 @@
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#define __ASM_MIPS_MACH_RM_WAR_H
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#endif /* __ASM_MIPS_MACH_RM_WAR_H */
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@ -15,12 +15,10 @@ extern int sb1250_m3_workaround_needed(void);
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#endif
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#define BCM1250_M3_WAR sb1250_m3_workaround_needed()
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#define SIBYTE_1956_WAR 1
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#else
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#endif
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@ -9,6 +9,5 @@
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#define __ASM_MIPS_MACH_TX49XX_WAR_H
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#define BCM1250_M3_WAR 0
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#define SIBYTE_1956_WAR 0
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#endif /* __ASM_MIPS_MACH_TX49XX_WAR_H */
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@ -86,11 +86,4 @@
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#error Check setting of BCM1250_M3_WAR for your platform
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#endif
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/*
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* This is a DUART workaround related to glitches around register accesses
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*/
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#ifndef SIBYTE_1956_WAR
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#error Check setting of SIBYTE_1956_WAR for your platform
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#endif
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#endif /* _ASM_WAR_H */
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@ -35,7 +35,6 @@
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#include <linux/refcount.h>
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#include <asm/io.h>
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#include <asm/war.h>
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#include <asm/sibyte/sb1250.h>
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#include <asm/sibyte/sb1250_uart.h>
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@ -157,7 +156,7 @@ static unsigned char read_sbdchn(struct sbd_port *sport, int reg)
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unsigned char retval;
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retval = __read_sbdchn(sport, reg);
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if (SIBYTE_1956_WAR)
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if (IS_ENABLED(CONFIG_SB1_PASS_2_WORKAROUNDS))
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__war_sbd1956(sport);
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return retval;
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}
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@ -167,7 +166,7 @@ static unsigned char read_sbdshr(struct sbd_port *sport, int reg)
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unsigned char retval;
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retval = __read_sbdshr(sport, reg);
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if (SIBYTE_1956_WAR)
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if (IS_ENABLED(CONFIG_SB1_PASS_2_WORKAROUNDS))
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__war_sbd1956(sport);
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return retval;
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}
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@ -175,14 +174,14 @@ static unsigned char read_sbdshr(struct sbd_port *sport, int reg)
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static void write_sbdchn(struct sbd_port *sport, int reg, unsigned int value)
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{
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__write_sbdchn(sport, reg, value);
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if (SIBYTE_1956_WAR)
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if (IS_ENABLED(CONFIG_SB1_PASS_2_WORKAROUNDS))
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__war_sbd1956(sport);
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}
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static void write_sbdshr(struct sbd_port *sport, int reg, unsigned int value)
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{
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__write_sbdshr(sport, reg, value);
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if (SIBYTE_1956_WAR)
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if (IS_ENABLED(CONFIG_SB1_PASS_2_WORKAROUNDS))
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__war_sbd1956(sport);
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}
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