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MIPS: Convert MIPS34K_MISSED_ITLB_WAR into a config option

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Use a new config option to enable MIPS 34K ITLB workaround and remove
define from different war.h files.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Thomas Bogendoerfer 2020-08-24 18:32:50 +02:00
parent 256ec489f1
commit a7fbed988f
15 changed files with 6 additions and 22 deletions
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4
arch/mips/Kconfig
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@ -2683,6 +2683,10 @@ config WAR_ICACHE_REFILLS
config WAR_R10000_LLSC
bool
# 34K core erratum: "Problems Executing the TLBR Instruction"
config WAR_MIPS34K_MISSED_ITLB
bool
#
# - Highmem only makes sense for the 32-bit kernel.
# - The current highmem code will only work properly on physically indexed

1
arch/mips/include/asm/mach-cavium-octeon/war.h
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@ -11,7 +11,6 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#define CAVIUM_OCTEON_DCACHE_PREFETCH_WAR \
OCTEON_IS_MODEL(OCTEON_CN6XXX)

1
arch/mips/include/asm/mach-generic/war.h
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@ -10,6 +10,5 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MACH_GENERIC_WAR_H */

1
arch/mips/include/asm/mach-ip22/war.h
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@ -10,6 +10,5 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_IP22_WAR_H */

1
arch/mips/include/asm/mach-ip27/war.h
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@ -10,6 +10,5 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_IP27_WAR_H */

1
arch/mips/include/asm/mach-ip28/war.h
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@ -10,6 +10,5 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_IP28_WAR_H */

1
arch/mips/include/asm/mach-ip30/war.h
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@ -7,6 +7,5 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_IP30_WAR_H */

1
arch/mips/include/asm/mach-ip32/war.h
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@ -10,6 +10,5 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_IP32_WAR_H */

1
arch/mips/include/asm/mach-malta/war.h
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@ -10,6 +10,5 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */

1
arch/mips/include/asm/mach-rc32434/war.h
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@ -10,6 +10,5 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */

1
arch/mips/include/asm/mach-rm/war.h
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@ -10,6 +10,5 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_RM_WAR_H */

2
arch/mips/include/asm/mach-sibyte/war.h
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@ -24,6 +24,4 @@ extern int sb1250_m3_workaround_needed(void);
#endif
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_SIBYTE_WAR_H */

1
arch/mips/include/asm/mach-tx49xx/war.h
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@ -10,6 +10,5 @@
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_TX49XX_WAR_H */

4
arch/mips/include/asm/mipsregs.h
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@ -2716,7 +2716,7 @@ static inline void tlb_probe(void)
static inline void tlb_read(void)
{
#if MIPS34K_MISSED_ITLB_WAR
#ifdef CONFIG_WAR_MIPS34K_MISSED_ITLB
int res = 0;
__asm__ __volatile__(
@ -2738,7 +2738,7 @@ static inline void tlb_read(void)
"tlbr\n\t"
".set reorder");
#if MIPS34K_MISSED_ITLB_WAR
#ifdef CONFIG_WAR_MIPS34K_MISSED_ITLB
if ((res & _ULCAST_(1)))
__asm__ __volatile__(
" .set push \n"

7
arch/mips/include/asm/war.h
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@ -93,11 +93,4 @@
#error Check setting of SIBYTE_1956_WAR for your platform
#endif
/*
* 34K core erratum: "Problems Executing the TLBR Instruction"
*/
#ifndef MIPS34K_MISSED_ITLB_WAR
#error Check setting of MIPS34K_MISSED_ITLB_WAR for your platform
#endif
#endif /* _ASM_WAR_H */