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drm/amd/display: correct eDP T9 delay

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[Why]
The current end of T9 delay is relay on polling
sink status by DPCD. But the polling for sink
status change after NoVideoStream_flag set to 0.

[How]
Add function edp_add_delay_for_T9 to add T9 delay.
Move the sink status polling after blank.

Signed-off-by: Hugo Hu <hugo.hu@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Hugo Hu
2020-10-06 17:21:00 +08:00
committed by Alex Deucher
parent cae78e0331
commit 3a372bed1e
3 changed files with 17 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
View File

@@ -156,6 +156,13 @@ void dp_enable_link_phy(
dp_receiver_power_ctrl(link, true);
}
void edp_add_delay_for_T9(struct dc_link *link)
{
if (link->local_sink &&
link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off > 0)
udelay(link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off * 1000);
}
bool edp_receiver_ready_T9(struct dc_link *link)
{
unsigned int tries = 0;
@@ -165,7 +172,7 @@ bool edp_receiver_ready_T9(struct dc_link *link)
result = core_link_read_dpcd(link, DP_EDP_DPCD_REV, &edpRev, sizeof(edpRev));
/* start from eDP version 1.2, SINK_STAUS indicate the sink is ready.*/
/* start from eDP version 1.2, SINK_STAUS indicate the sink is ready.*/
if (result == DC_OK && edpRev >= DP_EDP_12) {
do {
sinkstatus = 1;
@@ -178,10 +185,6 @@ bool edp_receiver_ready_T9(struct dc_link *link)
} while (++tries < 50);
}
if (link->local_sink &&
link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off > 0)
udelay(link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off * 1000);
return result;
}
bool edp_receiver_ready_T7(struct dc_link *link)

16
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
View File

@@ -992,8 +992,6 @@ void dce110_edp_backlight_control(
link_transmitter_control(ctx->dc_bios, &cntl);
if (enable && link->dpcd_sink_ext_caps.bits.oled)
msleep(OLED_POST_T7_DELAY);
@@ -1004,7 +1002,7 @@ void dce110_edp_backlight_control(
/*edp 1.2*/
if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF)
edp_receiver_ready_T9(link);
edp_add_delay_for_T9(link);
if (!enable && link->dpcd_sink_ext_caps.bits.oled)
msleep(OLED_PRE_T11_DELAY);
@@ -1145,12 +1143,14 @@ void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
/*
* After output is idle pattern some sinks need time to recognize the stream
* has changed or they enter protection state and hang.
*/
if (!dc_is_embedded_signal(pipe_ctx->stream->signal))
if (!dc_is_embedded_signal(pipe_ctx->stream->signal)) {
/*
* After output is idle pattern some sinks need time to recognize the stream
* has changed or they enter protection state and hang.
*/
msleep(60);
} else if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP)
edp_receiver_ready_T9(link);
}
}

1
drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
View File

@@ -51,6 +51,7 @@ void dp_enable_link_phy(
const struct dc_link_settings *link_settings);
void dp_receiver_power_ctrl(struct dc_link *link, bool on);
void edp_add_delay_for_T9(struct dc_link *link);
bool edp_receiver_ready_T9(struct dc_link *link);
bool edp_receiver_ready_T7(struct dc_link *link);