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Merge tag 'amd-drm-next-5.18-2022-02-25' of https://gitlab.freedesktop.org/agd5f/linux into drm-next

Browse Source 
amd-drm-next-5.18-2022-02-25:

amdgpu:
- Raven2 suspend/resume fix
- SDMA 5.2.6 updates
- VCN 3.1.2 updates
- SMU 13.0.5 updates
- DCN 3.1.5 updates
- Virtual display fixes
- SMU code cleanup
- Harvest fixes
- Expose benchmark tests via debugfs
- Drop no longer relevant gart aperture tests
- More RAS restructuring
- W=1 fixes
- PSR rework
- DP/VGA adapter fixes
- DP MST fixes
- GPUVM eviction fix
- GPU reset debugfs register dumping support
- Misc display fixes
- SR-IOV fix
- Aldebaran mGPU fix
- Add module parameter to disable XGMI for testing

amdkfd:
- IH ring overflow logging fixes
- CRIU fixes
- Misc fixes

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220225183535.5907-1-alexander.deucher@amd.com
This commit is contained in:
Dave Airlie 2022-03-01 16:19:02 +10:00
commit 38a15ad948
110 changed files with 201294 additions and 714 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/amd/amdgpu/Makefile
View File

@ -46,7 +46,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
atom.o amdgpu_fence.o amdgpu_ttm.o amdgpu_object.o amdgpu_gart.o \
amdgpu_encoders.o amdgpu_display.o amdgpu_i2c.o \
amdgpu_gem.o amdgpu_ring.o \
amdgpu_cs.o amdgpu_bios.o amdgpu_benchmark.o amdgpu_test.o \
amdgpu_cs.o amdgpu_bios.o amdgpu_benchmark.o \
atombios_dp.o amdgpu_afmt.o amdgpu_trace_points.o \
atombios_encoders.o amdgpu_sa.o atombios_i2c.o \
amdgpu_dma_buf.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \

17
drivers/gpu/drm/amd/amdgpu/amdgpu.h
View File

@ -155,8 +155,6 @@ extern int amdgpu_vis_vram_limit;
extern int amdgpu_gart_size;
extern int amdgpu_gtt_size;
extern int amdgpu_moverate;
extern int amdgpu_benchmarking;
extern int amdgpu_testing;
extern int amdgpu_audio;
extern int amdgpu_disp_priority;
extern int amdgpu_hw_i2c;
@ -213,6 +211,7 @@ extern int amdgpu_mes;
extern int amdgpu_noretry;
extern int amdgpu_force_asic_type;
extern int amdgpu_smartshift_bias;
extern int amdgpu_use_xgmi_p2p;
#ifdef CONFIG_HSA_AMD
extern int sched_policy;
extern bool debug_evictions;
@ -586,13 +585,7 @@ void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
/*
* Benchmarking
*/
void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
/*
* Testing
*/
void amdgpu_test_moves(struct amdgpu_device *adev);
int amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
/*
* ASIC specific register table accessible by UMD
@ -1102,6 +1095,12 @@ struct amdgpu_device {
struct ip_discovery_top *ip_top;
struct amdgpu_reset_domain *reset_domain;
struct mutex benchmark_mutex;
/* reset dump register */
uint32_t *reset_dump_reg_list;
int num_regs;
};
static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)

244
drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
View File

@ -29,14 +29,13 @@
#define AMDGPU_BENCHMARK_COMMON_MODES_N 17
static int amdgpu_benchmark_do_move(struct amdgpu_device *adev, unsigned size,
uint64_t saddr, uint64_t daddr, int n)
uint64_t saddr, uint64_t daddr, int n, s64 *time_ms)
{
unsigned long start_jiffies;
unsigned long end_jiffies;
ktime_t stime, etime;
struct dma_fence *fence;
int i, r;
start_jiffies = jiffies;
stime = ktime_get();
for (i = 0; i < n; i++) {
struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
r = amdgpu_copy_buffer(ring, saddr, daddr, size, NULL, &fence,
@ -48,120 +47,81 @@ static int amdgpu_benchmark_do_move(struct amdgpu_device *adev, unsigned size,
if (r)
goto exit_do_move;
}
end_jiffies = jiffies;
r = jiffies_to_msecs(end_jiffies - start_jiffies);
exit_do_move:
etime = ktime_get();
*time_ms = ktime_ms_delta(etime, stime);
return r;
}
static void amdgpu_benchmark_log_results(int n, unsigned size,
unsigned int time,
static void amdgpu_benchmark_log_results(struct amdgpu_device *adev,
int n, unsigned size,
s64 time_ms,
unsigned sdomain, unsigned ddomain,
char *kind)
{
unsigned int throughput = (n * (size >> 10)) / time;
DRM_INFO("amdgpu: %s %u bo moves of %u kB from"
" %d to %d in %u ms, throughput: %u Mb/s or %u MB/s\n",
kind, n, size >> 10, sdomain, ddomain, time,
s64 throughput = (n * (size >> 10));
throughput = div64_s64(throughput, time_ms);
dev_info(adev->dev, "amdgpu: %s %u bo moves of %u kB from"
" %d to %d in %lld ms, throughput: %lld Mb/s or %lld MB/s\n",
kind, n, size >> 10, sdomain, ddomain, time_ms,
throughput * 8, throughput);
}
static void amdgpu_benchmark_move(struct amdgpu_device *adev, unsigned size,
unsigned sdomain, unsigned ddomain)
static int amdgpu_benchmark_move(struct amdgpu_device *adev, unsigned size,
unsigned sdomain, unsigned ddomain)
{
struct amdgpu_bo *dobj = NULL;
struct amdgpu_bo *sobj = NULL;
struct amdgpu_bo_param bp;
uint64_t saddr, daddr;
s64 time_ms;
int r, n;
int time;
memset(&bp, 0, sizeof(bp));
bp.size = size;
bp.byte_align = PAGE_SIZE;
bp.domain = sdomain;
bp.flags = 0;
bp.type = ttm_bo_type_kernel;
bp.resv = NULL;
bp.bo_ptr_size = sizeof(struct amdgpu_bo);
n = AMDGPU_BENCHMARK_ITERATIONS;
r = amdgpu_bo_create(adev, &bp, &sobj);
if (r) {
r = amdgpu_bo_create_kernel(adev, size,
PAGE_SIZE, sdomain,
&sobj,
&saddr,
NULL);
if (r)
goto out_cleanup;
}
r = amdgpu_bo_reserve(sobj, false);
if (unlikely(r != 0))
r = amdgpu_bo_create_kernel(adev, size,
PAGE_SIZE, ddomain,
&dobj,
&daddr,
NULL);
if (r)
goto out_cleanup;
r = amdgpu_bo_pin(sobj, sdomain);
if (r) {
amdgpu_bo_unreserve(sobj);
goto out_cleanup;
}
r = amdgpu_ttm_alloc_gart(&sobj->tbo);
amdgpu_bo_unreserve(sobj);
if (r) {
goto out_cleanup;
}
saddr = amdgpu_bo_gpu_offset(sobj);
bp.domain = ddomain;
r = amdgpu_bo_create(adev, &bp, &dobj);
if (r) {
goto out_cleanup;
}
r = amdgpu_bo_reserve(dobj, false);
if (unlikely(r != 0))
goto out_cleanup;
r = amdgpu_bo_pin(dobj, ddomain);
if (r) {
amdgpu_bo_unreserve(sobj);
goto out_cleanup;
}
r = amdgpu_ttm_alloc_gart(&dobj->tbo);
amdgpu_bo_unreserve(dobj);
if (r) {
goto out_cleanup;
}
daddr = amdgpu_bo_gpu_offset(dobj);
if (adev->mman.buffer_funcs) {
time = amdgpu_benchmark_do_move(adev, size, saddr, daddr, n);
if (time < 0)
r = amdgpu_benchmark_do_move(adev, size, saddr, daddr, n, &time_ms);
if (r)
goto out_cleanup;
if (time > 0)
amdgpu_benchmark_log_results(n, size, time,
else
amdgpu_benchmark_log_results(adev, n, size, time_ms,
sdomain, ddomain, "dma");
}
out_cleanup:
/* Check error value now. The value can be overwritten when clean up.*/
if (r) {
DRM_ERROR("Error while benchmarking BO move.\n");
}
if (r < 0)
dev_info(adev->dev, "Error while benchmarking BO move.\n");
if (sobj) {
r = amdgpu_bo_reserve(sobj, true);
if (likely(r == 0)) {
amdgpu_bo_unpin(sobj);
amdgpu_bo_unreserve(sobj);
}
amdgpu_bo_unref(&sobj);
}
if (dobj) {
r = amdgpu_bo_reserve(dobj, true);
if (likely(r == 0)) {
amdgpu_bo_unpin(dobj);
amdgpu_bo_unreserve(dobj);
}
amdgpu_bo_unref(&dobj);
}
if (sobj)
amdgpu_bo_free_kernel(&sobj, &saddr, NULL);
if (dobj)
amdgpu_bo_free_kernel(&dobj, &daddr, NULL);
return r;
}
void amdgpu_benchmark(struct amdgpu_device *adev, int test_number)
int amdgpu_benchmark(struct amdgpu_device *adev, int test_number)
{
int i;
int i, r;
static const int common_modes[AMDGPU_BENCHMARK_COMMON_MODES_N] = {
640 * 480 * 4,
720 * 480 * 4,
@ -182,63 +142,119 @@ void amdgpu_benchmark(struct amdgpu_device *adev, int test_number)
1920 * 1200 * 4
};
mutex_lock(&adev->benchmark_mutex);
switch (test_number) {
case 1:
dev_info(adev->dev,
"benchmark test: %d (simple test, VRAM to GTT and GTT to VRAM)\n",
test_number);
/* simple test, VRAM to GTT and GTT to VRAM */
amdgpu_benchmark_move(adev, 1024*1024, AMDGPU_GEM_DOMAIN_GTT,
AMDGPU_GEM_DOMAIN_VRAM);
amdgpu_benchmark_move(adev, 1024*1024, AMDGPU_GEM_DOMAIN_VRAM,
AMDGPU_GEM_DOMAIN_GTT);
r = amdgpu_benchmark_move(adev, 1024*1024, AMDGPU_GEM_DOMAIN_GTT,
AMDGPU_GEM_DOMAIN_VRAM);
if (r)
goto done;
r = amdgpu_benchmark_move(adev, 1024*1024, AMDGPU_GEM_DOMAIN_VRAM,
AMDGPU_GEM_DOMAIN_GTT);
if (r)
goto done;
break;
case 2:
dev_info(adev->dev,
"benchmark test: %d (simple test, VRAM to VRAM)\n",
test_number);
/* simple test, VRAM to VRAM */
amdgpu_benchmark_move(adev, 1024*1024, AMDGPU_GEM_DOMAIN_VRAM,
AMDGPU_GEM_DOMAIN_VRAM);
r = amdgpu_benchmark_move(adev, 1024*1024, AMDGPU_GEM_DOMAIN_VRAM,
AMDGPU_GEM_DOMAIN_VRAM);
if (r)
goto done;
break;
case 3:
dev_info(adev->dev,
"benchmark test: %d (GTT to VRAM, buffer size sweep, powers of 2)\n",
test_number);
/* GTT to VRAM, buffer size sweep, powers of 2 */
for (i = 1; i <= 16384; i <<= 1)
amdgpu_benchmark_move(adev, i * AMDGPU_GPU_PAGE_SIZE,
AMDGPU_GEM_DOMAIN_GTT,
AMDGPU_GEM_DOMAIN_VRAM);
for (i = 1; i <= 16384; i <<= 1) {
r = amdgpu_benchmark_move(adev, i * AMDGPU_GPU_PAGE_SIZE,
AMDGPU_GEM_DOMAIN_GTT,
AMDGPU_GEM_DOMAIN_VRAM);
if (r)
goto done;
}
break;
case 4:
dev_info(adev->dev,
"benchmark test: %d (VRAM to GTT, buffer size sweep, powers of 2)\n",
test_number);
/* VRAM to GTT, buffer size sweep, powers of 2 */
for (i = 1; i <= 16384; i <<= 1)
amdgpu_benchmark_move(adev, i * AMDGPU_GPU_PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM,
AMDGPU_GEM_DOMAIN_GTT);
for (i = 1; i <= 16384; i <<= 1) {
r = amdgpu_benchmark_move(adev, i * AMDGPU_GPU_PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM,
AMDGPU_GEM_DOMAIN_GTT);
if (r)
goto done;
}
break;
case 5:
dev_info(adev->dev,
"benchmark test: %d (VRAM to VRAM, buffer size sweep, powers of 2)\n",
test_number);
/* VRAM to VRAM, buffer size sweep, powers of 2 */
for (i = 1; i <= 16384; i <<= 1)
amdgpu_benchmark_move(adev, i * AMDGPU_GPU_PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM,
AMDGPU_GEM_DOMAIN_VRAM);
for (i = 1; i <= 16384; i <<= 1) {
r = amdgpu_benchmark_move(adev, i * AMDGPU_GPU_PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM,
AMDGPU_GEM_DOMAIN_VRAM);
if (r)
goto done;
}
break;
case 6:
dev_info(adev->dev,
"benchmark test: %d (GTT to VRAM, buffer size sweep, common modes)\n",
test_number);
/* GTT to VRAM, buffer size sweep, common modes */
for (i = 0; i < AMDGPU_BENCHMARK_COMMON_MODES_N; i++)
amdgpu_benchmark_move(adev, common_modes[i],
AMDGPU_GEM_DOMAIN_GTT,
AMDGPU_GEM_DOMAIN_VRAM);
for (i = 0; i < AMDGPU_BENCHMARK_COMMON_MODES_N; i++) {
r = amdgpu_benchmark_move(adev, common_modes[i],
AMDGPU_GEM_DOMAIN_GTT,
AMDGPU_GEM_DOMAIN_VRAM);
if (r)
goto done;
}
break;
case 7:
dev_info(adev->dev,
"benchmark test: %d (VRAM to GTT, buffer size sweep, common modes)\n",
test_number);
/* VRAM to GTT, buffer size sweep, common modes */
for (i = 0; i < AMDGPU_BENCHMARK_COMMON_MODES_N; i++)
amdgpu_benchmark_move(adev, common_modes[i],
AMDGPU_GEM_DOMAIN_VRAM,
AMDGPU_GEM_DOMAIN_GTT);
for (i = 0; i < AMDGPU_BENCHMARK_COMMON_MODES_N; i++) {
r = amdgpu_benchmark_move(adev, common_modes[i],
AMDGPU_GEM_DOMAIN_VRAM,
AMDGPU_GEM_DOMAIN_GTT);
if (r)
goto done;
}
break;
case 8:
dev_info(adev->dev,
"benchmark test: %d (VRAM to VRAM, buffer size sweep, common modes)\n",
test_number);
/* VRAM to VRAM, buffer size sweep, common modes */
for (i = 0; i < AMDGPU_BENCHMARK_COMMON_MODES_N; i++)
amdgpu_benchmark_move(adev, common_modes[i],
for (i = 0; i < AMDGPU_BENCHMARK_COMMON_MODES_N; i++) {
r = amdgpu_benchmark_move(adev, common_modes[i],
AMDGPU_GEM_DOMAIN_VRAM,
AMDGPU_GEM_DOMAIN_VRAM);
if (r)
goto done;
}
break;
default:
DRM_ERROR("Unknown benchmark\n");
dev_info(adev->dev, "Unknown benchmark %d\n", test_number);
r = -EINVAL;
break;
}
done:
mutex_unlock(&adev->benchmark_mutex);
return r;
}

105
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
View File

@ -1364,6 +1364,25 @@ static int amdgpu_debugfs_evict_gtt(void *data, u64 *val)
return 0;
}
static int amdgpu_debugfs_benchmark(void *data, u64 val)
{
struct amdgpu_device *adev = (struct amdgpu_device *)data;
struct drm_device *dev = adev_to_drm(adev);
int r;
r = pm_runtime_get_sync(dev->dev);
if (r < 0) {
pm_runtime_put_autosuspend(dev->dev);
return r;
}
r = amdgpu_benchmark(adev, val);
pm_runtime_mark_last_busy(dev->dev);
pm_runtime_put_autosuspend(dev->dev);
return r;
}
static int amdgpu_debugfs_vm_info_show(struct seq_file *m, void *unused)
{
@ -1400,6 +1419,8 @@ DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_evict_vram_fops, amdgpu_debugfs_evict_vram,
NULL, "%lld\n");
DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_evict_gtt_fops, amdgpu_debugfs_evict_gtt,
NULL, "%lld\n");
DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_benchmark_fops, NULL, amdgpu_debugfs_benchmark,
"%lld\n");
static void amdgpu_ib_preempt_fences_swap(struct amdgpu_ring *ring,
struct dma_fence **fences)
@ -1619,6 +1640,86 @@ DEFINE_DEBUGFS_ATTRIBUTE(fops_ib_preempt, NULL,
DEFINE_DEBUGFS_ATTRIBUTE(fops_sclk_set, NULL,
amdgpu_debugfs_sclk_set, "%llu\n");
static ssize_t amdgpu_reset_dump_register_list_read(struct file *f,
char __user *buf, size_t size, loff_t *pos)
{
struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
char reg_offset[12];
int i, ret, len = 0;
if (*pos)
return 0;
memset(reg_offset, 0, 12);
ret = down_read_killable(&adev->reset_domain->sem);
if (ret)
return ret;
for (i = 0; i < adev->num_regs; i++) {
sprintf(reg_offset, "0x%x\n", adev->reset_dump_reg_list[i]);
up_read(&adev->reset_domain->sem);
if (copy_to_user(buf + len, reg_offset, strlen(reg_offset)))
return -EFAULT;
len += strlen(reg_offset);
ret = down_read_killable(&adev->reset_domain->sem);
if (ret)
return ret;
}
up_read(&adev->reset_domain->sem);
*pos += len;
return len;
}
static ssize_t amdgpu_reset_dump_register_list_write(struct file *f,
const char __user *buf, size_t size, loff_t *pos)
{
struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
char reg_offset[11];
uint32_t *tmp;
int ret, i = 0, len = 0;
do {
memset(reg_offset, 0, 11);
if (copy_from_user(reg_offset, buf + len,
min(10, ((int)size-len)))) {
ret = -EFAULT;
goto error_free;
}
tmp = krealloc_array(tmp, i + 1, sizeof(uint32_t), GFP_KERNEL);
if (sscanf(reg_offset, "%X %n", &tmp[i], &ret) != 1) {
ret = -EINVAL;
goto error_free;
}
len += ret;
i++;
} while (len < size);
ret = down_write_killable(&adev->reset_domain->sem);
if (ret)
goto error_free;
swap(adev->reset_dump_reg_list, tmp);
adev->num_regs = i;
up_write(&adev->reset_domain->sem);
ret = size;
error_free:
kfree(tmp);
return ret;
}
static const struct file_operations amdgpu_reset_dump_register_list = {
.owner = THIS_MODULE,
.read = amdgpu_reset_dump_register_list_read,
.write = amdgpu_reset_dump_register_list_write,
.llseek = default_llseek
};
int amdgpu_debugfs_init(struct amdgpu_device *adev)
{
struct dentry *root = adev_to_drm(adev)->primary->debugfs_root;
@ -1685,6 +1786,10 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev)
&amdgpu_debugfs_test_ib_fops);
debugfs_create_file("amdgpu_vm_info", 0444, root, adev,
&amdgpu_debugfs_vm_info_fops);
debugfs_create_file("amdgpu_benchmark", 0200, root, adev,
&amdgpu_benchmark_fops);
debugfs_create_file("amdgpu_reset_dump_register_list", 0644, root, adev,
&amdgpu_reset_dump_register_list);
adev->debugfs_vbios_blob.data = adev->bios;
adev->debugfs_vbios_blob.size = adev->bios_size;

36
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
View File

@ -1539,6 +1539,11 @@ static int amdgpu_device_check_arguments(struct amdgpu_device *adev)
amdgpu_sched_hw_submission = roundup_pow_of_two(amdgpu_sched_hw_submission);
}
if (amdgpu_reset_method < -1 || amdgpu_reset_method > 4) {
dev_warn(adev->dev, "invalid option for reset method, reverting to default\n");
amdgpu_reset_method = -1;
}
amdgpu_device_check_smu_prv_buffer_size(adev);
amdgpu_device_check_vm_size(adev);
@ -3609,6 +3614,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
mutex_init(&adev->psp.mutex);
mutex_init(&adev->notifier_lock);
mutex_init(&adev->pm.stable_pstate_ctx_lock);
mutex_init(&adev->benchmark_mutex);
amdgpu_device_init_apu_flags(adev);
@ -3872,19 +3878,6 @@ fence_driver_init:
} else
adev->ucode_sysfs_en = true;
if ((amdgpu_testing & 1)) {
if (adev->accel_working)
amdgpu_test_moves(adev);
else
DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
}
if (amdgpu_benchmarking) {
if (adev->accel_working)
amdgpu_benchmark(adev, amdgpu_benchmarking);
else
DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
}
/*
* Register gpu instance before amdgpu_device_enable_mgpu_fan_boost.
* Otherwise the mgpu fan boost feature will be skipped due to the
@ -4723,6 +4716,22 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
return r;
}
static int amdgpu_reset_reg_dumps(struct amdgpu_device *adev)
{
uint32_t reg_value;
int i;
lockdep_assert_held(&adev->reset_domain->sem);
dump_stack();
for (i = 0; i < adev->num_regs; i++) {
reg_value = RREG32(adev->reset_dump_reg_list[i]);
trace_amdgpu_reset_reg_dumps(adev->reset_dump_reg_list[i], reg_value);
}
return 0;
}
int amdgpu_do_asic_reset(struct list_head *device_list_handle,
struct amdgpu_reset_context *reset_context)
{
@ -4733,6 +4742,7 @@ int amdgpu_do_asic_reset(struct list_head *device_list_handle,
/* Try reset handler method first */
tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
reset_list);
amdgpu_reset_reg_dumps(tmp_adev);
r = amdgpu_reset_perform_reset(tmp_adev, reset_context);
/* If reset handler not implemented, continue; otherwise return */
if (r == -ENOSYS)

132
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
View File

@ -385,6 +385,87 @@ static int amdgpu_discovery_validate_ip(const struct ip *ip)
return 0;
}
static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev,
uint32_t *vcn_harvest_count)
{
struct binary_header *bhdr;
struct ip_discovery_header *ihdr;
struct die_header *dhdr;
struct ip *ip;
uint16_t die_offset, ip_offset, num_dies, num_ips;
int i, j;
bhdr = (struct binary_header *)adev->mman.discovery_bin;
ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
num_dies = le16_to_cpu(ihdr->num_dies);
/* scan harvest bit of all IP data structures */
for (i = 0; i < num_dies; i++) {
die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
num_ips = le16_to_cpu(dhdr->num_ips);
ip_offset = die_offset + sizeof(*dhdr);
for (j = 0; j < num_ips; j++) {
ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
if (amdgpu_discovery_validate_ip(ip))
goto next_ip;
if (le16_to_cpu(ip->harvest) == 1) {
switch (le16_to_cpu(ip->hw_id)) {
case VCN_HWID:
(*vcn_harvest_count)++;
if (ip->number_instance == 0)
adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0;
else
adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
break;
case DMU_HWID:
adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
break;
default:
break;
}
}
next_ip:
ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1);
}
}
}
static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev,
uint32_t *vcn_harvest_count)
{
struct binary_header *bhdr;
struct harvest_table *harvest_info;
int i;
bhdr = (struct binary_header *)adev->mman.discovery_bin;
harvest_info = (struct harvest_table *)(adev->mman.discovery_bin +
le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset));
for (i = 0; i < 32; i++) {
if (le16_to_cpu(harvest_info->list[i].hw_id) == 0)
break;
switch (le16_to_cpu(harvest_info->list[i].hw_id)) {
case VCN_HWID:
(*vcn_harvest_count)++;
if (harvest_info->list[i].number_instance == 0)
adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0;
else
adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
break;
case DMU_HWID:
adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
break;
default:
break;
}
}
}
/* ================================================== */
struct ip_hw_instance {
@ -1041,32 +1122,26 @@ int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int n
void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
{
struct binary_header *bhdr;
struct harvest_table *harvest_info;
int i, vcn_harvest_count = 0;
int vcn_harvest_count = 0;
bhdr = (struct binary_header *)adev->mman.discovery_bin;
harvest_info = (struct harvest_table *)(adev->mman.discovery_bin +
le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset));
for (i = 0; i < 32; i++) {
if (le16_to_cpu(harvest_info->list[i].hw_id) == 0)
break;
switch (le16_to_cpu(harvest_info->list[i].hw_id)) {
case VCN_HWID:
vcn_harvest_count++;
if (harvest_info->list[i].number_instance == 0)
adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0;
else
adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
break;
case DMU_HWID:
adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
break;
default:
break;
}
/*
* Harvest table does not fit Navi1x and legacy GPUs,
* so read harvest bit per IP data structure to set
* harvest configuration.
*/
if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 2, 0)) {
if ((adev->pdev->device == 0x731E &&
(adev->pdev->revision == 0xC6 ||
adev->pdev->revision == 0xC7)) ||
(adev->pdev->device == 0x7340 &&
adev->pdev->revision == 0xC9) ||
(adev->pdev->device == 0x7360 &&
adev->pdev->revision == 0xC7))
amdgpu_discovery_read_harvest_bit_per_ip(adev,
&vcn_harvest_count);
} else {
amdgpu_discovery_read_from_harvest_table(adev,
&vcn_harvest_count);
}
amdgpu_discovery_harvest_config_quirk(adev);
@ -1292,6 +1367,7 @@ static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev)
case IP_VERSION(13, 0, 1):
case IP_VERSION(13, 0, 2):
case IP_VERSION(13, 0, 3):
case IP_VERSION(13, 0, 5):
case IP_VERSION(13, 0, 8):
amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
break;
@ -1334,6 +1410,7 @@ static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev)
case IP_VERSION(13, 0, 1):
case IP_VERSION(13, 0, 2):
case IP_VERSION(13, 0, 3):
case IP_VERSION(13, 0, 5):
case IP_VERSION(13, 0, 8):
amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
break;
@ -1371,6 +1448,7 @@ static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev)
case IP_VERSION(3, 0, 1):
case IP_VERSION(3, 1, 2):
case IP_VERSION(3, 1, 3):
case IP_VERSION(3, 1, 5):
case IP_VERSION(3, 1, 6):
amdgpu_device_ip_block_add(adev, &dm_ip_block);
break;
@ -1458,6 +1536,7 @@ static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev)
case IP_VERSION(5, 2, 2):
case IP_VERSION(5, 2, 4):
case IP_VERSION(5, 2, 5):
case IP_VERSION(5, 2, 6):
case IP_VERSION(5, 2, 3):
case IP_VERSION(5, 2, 1):
case IP_VERSION(5, 2, 7):
@ -1527,6 +1606,7 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
case IP_VERSION(3, 0, 0):
case IP_VERSION(3, 0, 16):
case IP_VERSION(3, 1, 1):
case IP_VERSION(3, 1, 2):
case IP_VERSION(3, 0, 2):
case IP_VERSION(3, 0, 192):
amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
@ -1820,6 +1900,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
break;
case IP_VERSION(7, 2, 0):
case IP_VERSION(7, 2, 1):
case IP_VERSION(7, 3, 0):
case IP_VERSION(7, 5, 0):
case IP_VERSION(7, 5, 1):
adev->nbio.funcs = &nbio_v7_2_funcs;
@ -1905,6 +1986,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
case IP_VERSION(11, 5, 0):
case IP_VERSION(13, 0, 1):
case IP_VERSION(13, 0, 9):
case IP_VERSION(13, 0, 10):
adev->smuio.funcs = &smuio_v11_0_6_funcs;
break;
case IP_VERSION(13, 0, 2):

30
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
View File

@ -506,33 +506,9 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
*/
if ((bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
amdgpu_bo_support_uswc(bo_flags) &&
amdgpu_device_asic_has_dc_support(adev->asic_type)) {
switch (adev->asic_type) {
case CHIP_CARRIZO:
case CHIP_STONEY:
domain |= AMDGPU_GEM_DOMAIN_GTT;
break;
default:
switch (adev->ip_versions[DCE_HWIP][0]) {
case IP_VERSION(1, 0, 0):
case IP_VERSION(1, 0, 1):
/* enable S/G on PCO and RV2 */
if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
(adev->apu_flags & AMD_APU_IS_PICASSO))
domain |= AMDGPU_GEM_DOMAIN_GTT;
break;
case IP_VERSION(2, 1, 0):
case IP_VERSION(3, 0, 1):
case IP_VERSION(3, 1, 2):
case IP_VERSION(3, 1, 3):
domain |= AMDGPU_GEM_DOMAIN_GTT;
break;
default:
break;
}
break;
}
}
amdgpu_device_asic_has_dc_support(adev->asic_type) &&
adev->mode_info.gpu_vm_support)
domain |= AMDGPU_GEM_DOMAIN_GTT;
#endif
return domain;

30
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
View File

@ -110,8 +110,6 @@ int amdgpu_vis_vram_limit;
int amdgpu_gart_size = -1; /* auto */
int amdgpu_gtt_size = -1; /* auto */
int amdgpu_moverate = -1; /* auto */
int amdgpu_benchmarking;
int amdgpu_testing;
int amdgpu_audio = -1;
int amdgpu_disp_priority;
int amdgpu_hw_i2c;
@ -178,6 +176,7 @@ int amdgpu_tmz = -1; /* auto */
int amdgpu_reset_method = -1; /* auto */
int amdgpu_num_kcq = -1;
int amdgpu_smartshift_bias;
int amdgpu_use_xgmi_p2p = 1;
static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work);
@ -231,20 +230,6 @@ module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
module_param_named(moverate, amdgpu_moverate, int, 0600);
/**
* DOC: benchmark (int)
* Run benchmarks. The default is 0 (Skip benchmarks).
*/
MODULE_PARM_DESC(benchmark, "Run benchmark");
module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
/**
* DOC: test (int)
* Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test).
*/
MODULE_PARM_DESC(test, "Run tests");
module_param_named(test, amdgpu_testing, int, 0444);
/**
* DOC: audio (int)
* Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it.
@ -667,6 +652,13 @@ MODULE_PARM_DESC(force_asic_type,
"A non negative value used to specify the asic type for all supported GPUs");
module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444);
/**
* DOC: use_xgmi_p2p (int)
* Enables/disables XGMI P2P interface (0 = disable, 1 = enable).
*/
MODULE_PARM_DESC(use_xgmi_p2p,
"Enable XGMI P2P interface (0 = disable; 1 = enable (default))");
module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444);
#ifdef CONFIG_HSA_AMD
@ -740,7 +732,7 @@ MODULE_PARM_DESC(debug_largebar,
* systems with a broken CRAT table.
*
* Default is auto (according to asic type, iommu_v2, and crat table, to decide
* whehter use CRAT)
* whether use CRAT)
*/
int ignore_crat;
module_param(ignore_crat, int, 0444);
@ -845,9 +837,9 @@ module_param_named(tmz, amdgpu_tmz, int, 0444);
/**
* DOC: reset_method (int)
* GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco, 5 = pci)
* GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco)
*/
MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco, 5 = pci)");
MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)");
module_param_named(reset_method, amdgpu_reset_method, int, 0444);
/**

1
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
View File

@ -537,6 +537,7 @@ void amdgpu_gmc_tmz_set(struct amdgpu_device *adev)
case CHIP_NAVI12:
case CHIP_VANGOGH:
case CHIP_YELLOW_CARP:
case CHIP_IP_DISCOVERY:
/* Don't enable it by default yet.
*/
if (amdgpu_tmz < 1) {

1
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
View File

@ -341,6 +341,7 @@ struct amdgpu_mode_info {
int num_crtc; /* number of crtcs */
int num_hpd; /* number of hpd pins */
int num_dig; /* number of dig blocks */
bool gpu_vm_support; /* supports display from GTT */
int disp_priority;
const struct amdgpu_display_funcs *funcs;
const enum drm_plane_type *plane_type;

1
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
View File

@ -133,6 +133,7 @@ static int psp_early_init(void *handle)
break;
case IP_VERSION(13, 0, 1):
case IP_VERSION(13, 0, 3):
case IP_VERSION(13, 0, 5):
case IP_VERSION(13, 0, 8):
psp_v13_0_set_psp_funcs(psp);
psp->autoload_supported = true;

4
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
View File

@ -2400,7 +2400,7 @@ bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev)
int amdgpu_ras_block_late_init(struct amdgpu_device *adev,
struct ras_common_if *ras_block)
{
struct amdgpu_ras_block_object *ras_obj;
struct amdgpu_ras_block_object *ras_obj = NULL;
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
unsigned long ue_count, ce_count;
int r;
@ -2456,7 +2456,7 @@ cleanup:
return r;
}
int amdgpu_ras_block_late_init_default(struct amdgpu_device *adev,
static int amdgpu_ras_block_late_init_default(struct amdgpu_device *adev,
struct ras_common_if *ras_block)
{
return amdgpu_ras_block_late_init(adev, ras_block);

250
drivers/gpu/drm/amd/amdgpu/amdgpu_test.c
View File

@ -1,250 +0,0 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright 2009 VMware, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Michel Dänzer
*/
#include <drm/amdgpu_drm.h>
#include "amdgpu.h"
#include "amdgpu_uvd.h"
#include "amdgpu_vce.h"
/* Test BO GTT->VRAM and VRAM->GTT GPU copies across the whole GTT aperture */
static void amdgpu_do_test_moves(struct amdgpu_device *adev)
{
struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
struct amdgpu_bo *vram_obj = NULL;
struct amdgpu_bo **gtt_obj = NULL;
struct amdgpu_bo_param bp;
uint64_t gart_addr, vram_addr;
unsigned n, size;
int i, r;
size = 1024 * 1024;
/* Number of tests =
* (Total GTT - gart_pin_size - (2 transfer windows for buffer moves)) / test size
*/
n = adev->gmc.gart_size - atomic64_read(&adev->gart_pin_size);
n -= AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS *
AMDGPU_GPU_PAGE_SIZE;
n /= size;
gtt_obj = kcalloc(n, sizeof(*gtt_obj), GFP_KERNEL);
if (!gtt_obj) {
DRM_ERROR("Failed to allocate %d pointers\n", n);
r = 1;
goto out_cleanup;
}
memset(&bp, 0, sizeof(bp));
bp.size = size;
bp.byte_align = PAGE_SIZE;
bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
bp.flags = 0;
bp.type = ttm_bo_type_kernel;
bp.resv = NULL;
bp.bo_ptr_size = sizeof(struct amdgpu_bo);
r = amdgpu_bo_create(adev, &bp, &vram_obj);
if (r) {
DRM_ERROR("Failed to create VRAM object\n");
goto out_cleanup;
}
r = amdgpu_bo_reserve(vram_obj, false);
if (unlikely(r != 0))
goto out_unref;
r = amdgpu_bo_pin(vram_obj, AMDGPU_GEM_DOMAIN_VRAM);
if (r) {
DRM_ERROR("Failed to pin VRAM object\n");
goto out_unres;
}
vram_addr = amdgpu_bo_gpu_offset(vram_obj);
for (i = 0; i < n; i++) {
void *gtt_map, *vram_map;
void **gart_start, **gart_end;
void **vram_start, **vram_end;
struct dma_fence *fence = NULL;
bp.domain = AMDGPU_GEM_DOMAIN_GTT;
r = amdgpu_bo_create(adev, &bp, gtt_obj + i);
if (r) {
DRM_ERROR("Failed to create GTT object %d\n", i);
goto out_lclean;
}
r = amdgpu_bo_reserve(gtt_obj[i], false);
if (unlikely(r != 0))
goto out_lclean_unref;
r = amdgpu_bo_pin(gtt_obj[i], AMDGPU_GEM_DOMAIN_GTT);
if (r) {
DRM_ERROR("Failed to pin GTT object %d\n", i);
goto out_lclean_unres;
}
r = amdgpu_ttm_alloc_gart(&gtt_obj[i]->tbo);
if (r) {
DRM_ERROR("%p bind failed\n", gtt_obj[i]);
goto out_lclean_unpin;
}
gart_addr = amdgpu_bo_gpu_offset(gtt_obj[i]);
r = amdgpu_bo_kmap(gtt_obj[i], &gtt_map);
if (r) {
DRM_ERROR("Failed to map GTT object %d\n", i);
goto out_lclean_unpin;
}
for (gart_start = gtt_map, gart_end = gtt_map + size;
gart_start < gart_end;
gart_start++)
*gart_start = gart_start;
amdgpu_bo_kunmap(gtt_obj[i]);
r = amdgpu_copy_buffer(ring, gart_addr, vram_addr,
size, NULL, &fence, false, false, false);
if (r) {
DRM_ERROR("Failed GTT->VRAM copy %d\n", i);
goto out_lclean_unpin;
}
r = dma_fence_wait(fence, false);
if (r) {
DRM_ERROR("Failed to wait for GTT->VRAM fence %d\n", i);
goto out_lclean_unpin;
}
dma_fence_put(fence);
fence = NULL;
r = amdgpu_bo_kmap(vram_obj, &vram_map);
if (r) {
DRM_ERROR("Failed to map VRAM object after copy %d\n", i);
goto out_lclean_unpin;
}
for (gart_start = gtt_map, gart_end = gtt_map + size,
vram_start = vram_map, vram_end = vram_map + size;
vram_start < vram_end;
gart_start++, vram_start++) {
if (*vram_start != gart_start) {
DRM_ERROR("Incorrect GTT->VRAM copy %d: Got 0x%p, "
"expected 0x%p (GTT/VRAM offset "
"0x%16llx/0x%16llx)\n",
i, *vram_start, gart_start,
(unsigned long long)
(gart_addr - adev->gmc.gart_start +
(void *)gart_start - gtt_map),
(unsigned long long)
(vram_addr - adev->gmc.vram_start +
(void *)gart_start - gtt_map));
amdgpu_bo_kunmap(vram_obj);
goto out_lclean_unpin;
}
*vram_start = vram_start;
}
amdgpu_bo_kunmap(vram_obj);
r = amdgpu_copy_buffer(ring, vram_addr, gart_addr,
size, NULL, &fence, false, false, false);
if (r) {
DRM_ERROR("Failed VRAM->GTT copy %d\n", i);
goto out_lclean_unpin;
}
r = dma_fence_wait(fence, false);
if (r) {
DRM_ERROR("Failed to wait for VRAM->GTT fence %d\n", i);
goto out_lclean_unpin;
}
dma_fence_put(fence);
fence = NULL;
r = amdgpu_bo_kmap(gtt_obj[i], &gtt_map);
if (r) {
DRM_ERROR("Failed to map GTT object after copy %d\n", i);
goto out_lclean_unpin;
}
for (gart_start = gtt_map, gart_end = gtt_map + size,
vram_start = vram_map, vram_end = vram_map + size;
gart_start < gart_end;
gart_start++, vram_start++) {
if (*gart_start != vram_start) {
DRM_ERROR("Incorrect VRAM->GTT copy %d: Got 0x%p, "
"expected 0x%p (VRAM/GTT offset "
"0x%16llx/0x%16llx)\n",
i, *gart_start, vram_start,
(unsigned long long)
(vram_addr - adev->gmc.vram_start +
(void *)vram_start - vram_map),
(unsigned long long)
(gart_addr - adev->gmc.gart_start +
(void *)vram_start - vram_map));
amdgpu_bo_kunmap(gtt_obj[i]);
goto out_lclean_unpin;
}
}
amdgpu_bo_kunmap(gtt_obj[i]);
DRM_INFO("Tested GTT->VRAM and VRAM->GTT copy for GTT offset 0x%llx\n",
gart_addr - adev->gmc.gart_start);
continue;
out_lclean_unpin:
amdgpu_bo_unpin(gtt_obj[i]);
out_lclean_unres:
amdgpu_bo_unreserve(gtt_obj[i]);
out_lclean_unref:
amdgpu_bo_unref(&gtt_obj[i]);
out_lclean:
for (--i; i >= 0; --i) {
amdgpu_bo_unpin(gtt_obj[i]);
amdgpu_bo_unreserve(gtt_obj[i]);
amdgpu_bo_unref(&gtt_obj[i]);
}
if (fence)
dma_fence_put(fence);
break;
}
amdgpu_bo_unpin(vram_obj);
out_unres:
amdgpu_bo_unreserve(vram_obj);
out_unref:
amdgpu_bo_unref(&vram_obj);
out_cleanup:
kfree(gtt_obj);
if (r) {
pr_warn("Error while testing BO move\n");
}
}
void amdgpu_test_moves(struct amdgpu_device *adev)
{
if (adev->mman.buffer_funcs)
amdgpu_do_test_moves(adev);
}

16
drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
View File

@ -536,6 +536,22 @@ TRACE_EVENT(amdgpu_ib_pipe_sync,
__entry->seqno)
);
TRACE_EVENT(amdgpu_reset_reg_dumps,
TP_PROTO(uint32_t address, uint32_t value),
TP_ARGS(address, value),
TP_STRUCT__entry(
__field(uint32_t, address)
__field(uint32_t, value)
),
TP_fast_assign(
__entry->address = address;
__entry->value = value;
),
TP_printk("amdgpu register dump 0x%x: 0x%x",
__entry->address,
__entry->value)
);
#undef AMDGPU_JOB_GET_TIMELINE_NAME
#endif

8
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
View File

@ -51,6 +51,7 @@
#define FIRMWARE_ALDEBARAN "amdgpu/aldebaran_vcn.bin"
#define FIRMWARE_BEIGE_GOBY "amdgpu/beige_goby_vcn.bin"
#define FIRMWARE_YELLOW_CARP "amdgpu/yellow_carp_vcn.bin"
#define FIRMWARE_VCN_3_1_2 "amdgpu/vcn_3_1_2_vcn.bin"
MODULE_FIRMWARE(FIRMWARE_RAVEN);
MODULE_FIRMWARE(FIRMWARE_PICASSO);
@ -68,6 +69,7 @@ MODULE_FIRMWARE(FIRMWARE_VANGOGH);
MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH);
MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY);
MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP);
MODULE_FIRMWARE(FIRMWARE_VCN_3_1_2);
static void amdgpu_vcn_idle_work_handler(struct work_struct *work);
@ -165,6 +167,12 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
(adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
adev->vcn.indirect_sram = true;
break;
case IP_VERSION(3, 1, 2):
fw_name = FIRMWARE_VCN_3_1_2;
if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
(adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
adev->vcn.indirect_sram = true;
break;
default:
return -EINVAL;
}

3
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h
View File

@ -67,7 +67,8 @@ uint64_t amdgpu_xgmi_get_relative_phy_addr(struct amdgpu_device *adev,
static inline bool amdgpu_xgmi_same_hive(struct amdgpu_device *adev,
struct amdgpu_device *bo_adev)
{
return (adev != bo_adev &&
return (amdgpu_use_xgmi_p2p &&
adev != bo_adev &&
adev->gmc.xgmi.hive_id &&
adev->gmc.xgmi.hive_id == bo_adev->gmc.xgmi.hive_id);
}

3
drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
View File

@ -146,6 +146,9 @@ static void hdp_v4_0_init_registers(struct amdgpu_device *adev)
WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 4, 0))
WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, READ_BUFFER_WATERMARK, 2);
WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));
WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40));
}

4
drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
View File

@ -61,6 +61,7 @@ static u32 nbio_v7_2_get_rev_id(struct amdgpu_device *adev)
switch (adev->ip_versions[NBIO_HWIP][0]) {
case IP_VERSION(7, 2, 1):
case IP_VERSION(7, 3, 0):
case IP_VERSION(7, 5, 0):
tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC);
break;
@ -79,6 +80,7 @@ static void nbio_v7_2_mc_access_enable(struct amdgpu_device *adev, bool enable)
{
switch (adev->ip_versions[NBIO_HWIP][0]) {
case IP_VERSION(7, 2, 1):
case IP_VERSION(7, 3, 0):
case IP_VERSION(7, 5, 0):
if (enable)
WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC,
@ -262,6 +264,7 @@ static void nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev
switch (adev->ip_versions[NBIO_HWIP][0]) {
case IP_VERSION(7, 2, 1):
case IP_VERSION(7, 3, 0):
case IP_VERSION(7, 5, 0):
def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
@ -368,6 +371,7 @@ static void nbio_v7_2_init_registers(struct amdgpu_device *adev)
uint32_t def, data;
switch (adev->ip_versions[NBIO_HWIP][0]) {
case IP_VERSION(7, 2, 1):
case IP_VERSION(7, 3, 0):
case IP_VERSION(7, 5, 0):
def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3));
data = REG_SET_FIELD(data, BIF1_PCIE_MST_CTRL_3,

22
drivers/gpu/drm/amd/amdgpu/nv.c
View File

@ -204,6 +204,7 @@ static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
*codecs = &sc_video_codecs_decode;
return 0;
case IP_VERSION(3, 1, 1):
case IP_VERSION(3, 1, 2):
if (encode)
*codecs = &nv_video_codecs_encode;
else
@ -453,6 +454,8 @@ nv_asic_reset_method(struct amdgpu_device *adev)
case IP_VERSION(11, 5, 0):
case IP_VERSION(13, 0, 1):
case IP_VERSION(13, 0, 3):
case IP_VERSION(13, 0, 5):
case IP_VERSION(13, 0, 8):
return AMD_RESET_METHOD_MODE2;
case IP_VERSION(11, 0, 7):
case IP_VERSION(11, 0, 11):
@ -925,12 +928,25 @@ static int nv_common_early_init(void *handle)
AMD_CG_SUPPORT_HDP_LS |
AMD_CG_SUPPORT_ATHUB_MGCG |
AMD_CG_SUPPORT_ATHUB_LS |
AMD_CG_SUPPORT_IH_CG;
adev->pg_flags = AMD_PG_SUPPORT_GFX_PG;
AMD_CG_SUPPORT_IH_CG |
AMD_CG_SUPPORT_VCN_MGCG |
AMD_CG_SUPPORT_JPEG_MGCG;
adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
AMD_PG_SUPPORT_VCN |
AMD_PG_SUPPORT_VCN_DPG |
AMD_PG_SUPPORT_JPEG;
adev->external_rev_id = adev->rev_id + 0x01;
break;
case IP_VERSION(10, 3, 7):
adev->cg_flags = 0;
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_MGLS |
AMD_CG_SUPPORT_GFX_CGCG |
AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_GFX_3D_CGCG |
AMD_CG_SUPPORT_GFX_3D_CGLS |
AMD_CG_SUPPORT_GFX_RLC_LS |
AMD_CG_SUPPORT_GFX_CP_LS |
AMD_CG_SUPPORT_GFX_FGCG;
adev->pg_flags = AMD_PG_SUPPORT_VCN |
AMD_PG_SUPPORT_VCN_DPG |
AMD_PG_SUPPORT_JPEG;

7
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
View File

@ -34,6 +34,9 @@ MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin");
MODULE_FIRMWARE("amdgpu/yellow_carp_asd.bin");
MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin");
MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin");
MODULE_FIRMWARE("amdgpu/psp_13_0_5_asd.bin");
MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin");
MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin");
MODULE_FIRMWARE("amdgpu/psp_13_0_8_asd.bin");
MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin");
MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin");
@ -58,6 +61,9 @@ static int psp_v13_0_init_microcode(struct psp_context *psp)
case IP_VERSION(13, 0, 3):
chip_name = "yellow_carp";
break;
case IP_VERSION(13, 0, 5):
chip_name = "psp_13_0_5";
break;
case IP_VERSION(13, 0, 8):
chip_name = "psp_13_0_8";
break;
@ -75,6 +81,7 @@ static int psp_v13_0_init_microcode(struct psp_context *psp)
break;
case IP_VERSION(13, 0, 1):
case IP_VERSION(13, 0, 3):
case IP_VERSION(13, 0, 5):
case IP_VERSION(13, 0, 8):
err = psp_init_asd_microcode(psp, chip_name);
if (err)

11
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
View File

@ -51,6 +51,7 @@ MODULE_FIRMWARE("amdgpu/beige_goby_sdma.bin");
MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin");
MODULE_FIRMWARE("amdgpu/yellow_carp_sdma.bin");
MODULE_FIRMWARE("amdgpu/sdma_5_2_6.bin");
MODULE_FIRMWARE("amdgpu/sdma_5_2_7.bin");
#define SDMA1_REG_OFFSET 0x600
@ -156,10 +157,12 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
case IP_VERSION(5, 2, 3):
chip_name = "yellow_carp_sdma";
break;
case IP_VERSION(5, 2, 6):
chip_name = "sdma_5_2_6";
break;
case IP_VERSION(5, 2, 7):
chip_name = "sdma_5_2_7";
break;
default:
BUG();
}
@ -1622,6 +1625,7 @@ static int sdma_v5_2_set_clockgating_state(void *handle,
case IP_VERSION(5, 2, 1):
case IP_VERSION(5, 2, 4):
case IP_VERSION(5, 2, 5):
case IP_VERSION(5, 2, 6):
case IP_VERSION(5, 2, 3):
sdma_v5_2_update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE);
@ -1649,6 +1653,11 @@ static void sdma_v5_2_get_clockgating_state(void *handle, u32 *flags)
if (amdgpu_sriov_vf(adev))
*flags = 0;
/* AMD_CG_SUPPORT_SDMA_MGCG */
data = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));
if (!(data & SDMA0_CLK_CTRL__CGCG_EN_OVERRIDE_MASK))
*flags |= AMD_CG_SUPPORT_SDMA_MGCG;
/* AMD_CG_SUPPORT_SDMA_LS */
data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)

7
drivers/gpu/drm/amd/amdgpu/umc_v8_7.c
View File

@ -47,13 +47,6 @@ static inline uint32_t get_umc_v8_7_reg_offset(struct amdgpu_device *adev,
return adev->umc.channel_offs*ch_inst + UMC_8_INST_DIST*umc_inst;
}
static inline uint32_t get_umc_v8_7_channel_index(struct amdgpu_device *adev,
uint32_t umc_inst,
uint32_t ch_inst)
{
return adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst];
}
static void umc_v8_7_ecc_info_query_correctable_error_count(struct amdgpu_device *adev,
uint32_t umc_inst, uint32_t ch_inst,
unsigned long *error_count)

20
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
View File

@ -104,11 +104,6 @@ void kfd_chardev_exit(void)
kfd_device = NULL;
}
struct device *kfd_chardev(void)
{
return kfd_device;
}
static int kfd_open(struct inode *inode, struct file *filep)
{
@ -1215,8 +1210,15 @@ static int kfd_ioctl_map_memory_to_gpu(struct file *filep,
peer_pdd->dev->adev, (struct kgd_mem *)mem,
peer_pdd->drm_priv, &table_freed);
if (err) {
pr_err("Failed to map to gpu %d/%d\n",
i, args->n_devices);
struct pci_dev *pdev = peer_pdd->dev->adev->pdev;
dev_err(dev->adev->dev,
"Failed to map peer:%04x:%02x:%02x.%d mem_domain:%d\n",
pci_domain_nr(pdev->bus),
pdev->bus->number,
PCI_SLOT(pdev->devfn),
PCI_FUNC(pdev->devfn),
((struct kgd_mem *)mem)->domain);
goto map_memory_to_gpu_failed;
}
args->n_success = i+1;
@ -2097,8 +2099,8 @@ static int criu_restore_bos(struct kfd_process *p,
uint64_t *priv_offset,
uint64_t max_priv_data_size)
{
struct kfd_criu_bo_bucket *bo_buckets;
struct kfd_criu_bo_priv_data *bo_privs;
struct kfd_criu_bo_bucket *bo_buckets = NULL;
struct kfd_criu_bo_priv_data *bo_privs = NULL;
const bool criu_resume = true;
bool flush_tlbs = false;
int ret = 0, j = 0;

2
drivers/gpu/drm/amd/amdkfd/kfd_crat.c
View File

@ -1569,7 +1569,7 @@ int kfd_create_crat_image_acpi(void **crat_image, size_t *size)
/* Fetch the CRAT table from ACPI */
status = acpi_get_table(CRAT_SIGNATURE, 0, &crat_table);
if (status == AE_NOT_FOUND) {
pr_warn("CRAT table not found\n");
pr_info("CRAT table not found\n");
return -ENODATA;
} else if (ACPI_FAILURE(status)) {
const char *err = acpi_format_exception(status);

8
drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c
View File

@ -58,14 +58,14 @@ int kfd_interrupt_init(struct kfd_dev *kfd)
KFD_IH_NUM_ENTRIES * kfd->device_info.ih_ring_entry_size,
GFP_KERNEL);
if (r) {
dev_err(kfd_chardev(), "Failed to allocate IH fifo\n");
dev_err(kfd->adev->dev, "Failed to allocate IH fifo\n");
return r;
}
kfd->ih_wq = alloc_workqueue("KFD IH", WQ_HIGHPRI, 1);
if (unlikely(!kfd->ih_wq)) {
kfifo_free(&kfd->ih_fifo);
dev_err(kfd_chardev(), "Failed to allocate KFD IH workqueue\n");
dev_err(kfd->adev->dev, "Failed to allocate KFD IH workqueue\n");
return -ENOMEM;
}
spin_lock_init(&kfd->interrupt_lock);
@ -117,7 +117,7 @@ bool enqueue_ih_ring_entry(struct kfd_dev *kfd, const void *ih_ring_entry)
count = kfifo_in(&kfd->ih_fifo, ih_ring_entry,
kfd->device_info.ih_ring_entry_size);
if (count != kfd->device_info.ih_ring_entry_size) {
dev_err_ratelimited(kfd_chardev(),
dev_dbg_ratelimited(kfd->adev->dev,
"Interrupt ring overflow, dropping interrupt %d\n",
count);
return false;
@ -148,7 +148,7 @@ static void interrupt_wq(struct work_struct *work)
uint32_t ih_ring_entry[KFD_MAX_RING_ENTRY_SIZE];
if (dev->device_info.ih_ring_entry_size > sizeof(ih_ring_entry)) {
dev_err_once(kfd_chardev(), "Ring entry too small\n");
dev_err_once(dev->adev->dev, "Ring entry too small\n");
return;
}

1
drivers/gpu/drm/amd/amdkfd/kfd_priv.h
View File

@ -355,7 +355,6 @@ enum kfd_mempool {
/* Character device interface */
int kfd_chardev_init(void);
void kfd_chardev_exit(void);
struct device *kfd_chardev(void);
/**
* enum kfd_unmap_queues_filter - Enum for queue filters.

2
drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
View File

@ -786,7 +786,7 @@ int kfd_criu_restore_queue(struct kfd_process *p,
}
*priv_data_offset += sizeof(*q_data);
q_extra_data_size = q_data->ctl_stack_size + q_data->mqd_size;
q_extra_data_size = (uint64_t)q_data->ctl_stack_size + q_data->mqd_size;
if (*priv_data_offset + q_extra_data_size > max_priv_data_size) {
ret = -EINVAL;

61
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
View File

@ -114,6 +114,8 @@ MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
#define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
#define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin"
MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);
#define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"
MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);
@ -1441,6 +1443,25 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
switch (adev->ip_versions[DCE_HWIP][0]) {
case IP_VERSION(2, 1, 0):
switch (adev->dm.dmcub_fw_version) {
case 0: /* development */
case 0x1: /* linux-firmware.git hash 6d9f399 */
case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */
init_data.flags.disable_dmcu = false;
break;
default:
init_data.flags.disable_dmcu = true;
}
break;
case IP_VERSION(2, 0, 3):
init_data.flags.disable_dmcu = true;
break;
default:
break;
}
switch (adev->asic_type) {
case CHIP_CARRIZO:
case CHIP_STONEY:
@ -1448,34 +1469,29 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
break;
default:
switch (adev->ip_versions[DCE_HWIP][0]) {
case IP_VERSION(2, 1, 0):
init_data.flags.gpu_vm_support = true;
switch (adev->dm.dmcub_fw_version) {
case 0: /* development */
case 0x1: /* linux-firmware.git hash 6d9f399 */
case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */
init_data.flags.disable_dmcu = false;
break;
default:
init_data.flags.disable_dmcu = true;
}
break;
case IP_VERSION(1, 0, 0):
case IP_VERSION(1, 0, 1):
/* enable S/G on PCO and RV2 */
if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
(adev->apu_flags & AMD_APU_IS_PICASSO))
init_data.flags.gpu_vm_support = true;
break;
case IP_VERSION(2, 1, 0):
case IP_VERSION(3, 0, 1):
case IP_VERSION(3, 1, 2):
case IP_VERSION(3, 1, 3):
case IP_VERSION(3, 1, 5):
init_data.flags.gpu_vm_support = true;
break;
case IP_VERSION(2, 0, 3):
init_data.flags.disable_dmcu = true;
break;
default:
break;
}
break;
}
if (init_data.flags.gpu_vm_support)
adev->mode_info.gpu_vm_support = true;
if (amdgpu_dc_feature_mask & DC_FBC_MASK)
init_data.flags.fbc_support = true;
@ -1803,6 +1819,7 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
case IP_VERSION(3, 0, 1):
case IP_VERSION(3, 1, 2):
case IP_VERSION(3, 1, 3):
case IP_VERSION(3, 1, 5):
case IP_VERSION(3, 1, 6):
return 0;
default:
@ -1919,11 +1936,14 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;
fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
break;
case IP_VERSION(3, 1, 5):
dmub_asic = DMUB_ASIC_DCN315;
fw_name_dmub = FIRMWARE_DCN_315_DMUB;
break;
case IP_VERSION(3, 1, 6):
dmub_asic = DMUB_ASIC_DCN316;
fw_name_dmub = FIRMWARE_DCN316_DMUB;
break;
default:
/* ASIC doesn't support DMUB. */
return 0;
@ -4231,6 +4251,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
case IP_VERSION(3, 0, 0):
case IP_VERSION(3, 1, 2):
case IP_VERSION(3, 1, 3):
case IP_VERSION(3, 1, 5):
case IP_VERSION(3, 1, 6):
case IP_VERSION(2, 1, 0):
if (register_outbox_irq_handlers(dm->adev)) {
@ -4248,6 +4269,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
switch (adev->ip_versions[DCE_HWIP][0]) {
case IP_VERSION(3, 1, 2):
case IP_VERSION(3, 1, 3):
case IP_VERSION(3, 1, 5):
case IP_VERSION(3, 1, 6):
psr_feature_enabled = true;
break;
@ -4366,6 +4388,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
case IP_VERSION(3, 0, 1):
case IP_VERSION(3, 1, 2):
case IP_VERSION(3, 1, 3):
case IP_VERSION(3, 1, 5):
case IP_VERSION(3, 1, 6):
if (dcn10_register_irq_handlers(dm->adev)) {
DRM_ERROR("DM: Failed to initialize IRQ\n");
@ -4552,6 +4575,7 @@ static int dm_early_init(void *handle)
case IP_VERSION(2, 1, 0):
case IP_VERSION(3, 1, 2):
case IP_VERSION(3, 1, 3):
case IP_VERSION(3, 1, 5):
case IP_VERSION(3, 1, 6):
adev->mode_info.num_crtc = 4;
adev->mode_info.num_hpd = 4;
@ -5225,6 +5249,7 @@ get_plane_modifiers(const struct amdgpu_device *adev, unsigned int plane_type, u
case AMDGPU_FAMILY_NV:
case AMDGPU_FAMILY_VGH:
case AMDGPU_FAMILY_YC:
case AMDGPU_FAMILY_GC_10_3_6:
case AMDGPU_FAMILY_GC_10_3_7:
if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
add_gfx10_3_modifiers(adev, mods, &size, &capacity);
@ -6362,7 +6387,7 @@ static bool is_freesync_video_mode(const struct drm_display_mode *mode,
return true;
}
struct dc_stream_state *
static struct dc_stream_state *
create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
const struct drm_display_mode *drm_mode,
const struct dm_connector_state *dm_state,
@ -10192,7 +10217,7 @@ static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) {
dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
}
int dm_update_crtc_state(struct amdgpu_display_manager *dm,
static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
struct drm_atomic_state *state,
struct drm_crtc *crtc,
struct drm_crtc_state *old_crtc_state,

6
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
View File

@ -853,9 +853,9 @@ static int psr_capability_show(struct seq_file *m, void *data)
if (!(link->connector_signal & SIGNAL_TYPE_EDP))
return -ENODEV;
seq_printf(m, "Sink support: %s", str_yes_no(link->dpcd_caps.psr_caps.psr_version != 0));
if (link->dpcd_caps.psr_caps.psr_version)
seq_printf(m, " [0x%02x]", link->dpcd_caps.psr_caps.psr_version);
seq_printf(m, "Sink support: %s", str_yes_no(link->dpcd_caps.psr_info.psr_version != 0));
if (link->dpcd_caps.psr_info.psr_version)
seq_printf(m, " [0x%02x]", link->dpcd_caps.psr_info.psr_version);
seq_puts(m, "\n");
seq_printf(m, "Driver support: %s", str_yes_no(link->psr_settings.psr_feature_enabled));

1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
View File

@ -664,6 +664,7 @@ struct hdcp_workqueue *hdcp_create_workqueue(struct amdgpu_device *adev, struct
hdcp_work[i].hdcp.config.psp.handle = &adev->psp;
if (dc->ctx->dce_version == DCN_VERSION_3_1 ||
dc->ctx->dce_version == DCN_VERSION_3_15 ||
dc->ctx->dce_version == DCN_VERSION_3_16)
hdcp_work[i].hdcp.config.psp.caps.dtm_v3_supported = 1;
hdcp_work[i].hdcp.config.ddc.handle = dc_get_link_at_index(dc, i);

24
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
View File

@ -451,6 +451,7 @@ bool dm_helpers_dp_mst_stop_top_mgr(
struct dc_link *link)
{
struct amdgpu_dm_connector *aconnector = link->priv;
uint8_t i;
if (!aconnector) {
DRM_ERROR("Failed to find connector for link!");
@ -460,9 +461,26 @@ bool dm_helpers_dp_mst_stop_top_mgr(
DRM_INFO("DM_MST: stopping TM on aconnector: %p [id: %d]\n",
aconnector, aconnector->base.base.id);
if (aconnector->mst_mgr.mst_state == true)
if (aconnector->mst_mgr.mst_state == true) {
drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false);
for (i = 0; i < MAX_SINKS_PER_LINK; i++) {
if (link->remote_sinks[i] == NULL)
continue;
if (link->remote_sinks[i]->sink_signal ==
SIGNAL_TYPE_DISPLAY_PORT_MST) {
dc_link_remove_remote_sink(link, link->remote_sinks[i]);
if (aconnector->dc_sink) {
dc_sink_release(aconnector->dc_sink);
aconnector->dc_sink = NULL;
aconnector->dc_link->cur_link_settings.lane_count = 0;
}
}
}
}
return false;
}
@ -959,7 +977,9 @@ void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz)
// TODO
}
#if defined(CONFIG_DRM_AMD_DC_DCN)
void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable)
{
/* TODO: add peridic detection implementation */
/* TODO: add periodic detection implementation */
}
#endif

2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
View File

@ -213,7 +213,7 @@ static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnecto
return true;
}
bool retrieve_downstream_port_device(struct amdgpu_dm_connector *aconnector)
static bool retrieve_downstream_port_device(struct amdgpu_dm_connector *aconnector)
{
union dp_downstream_port_present ds_port_present;

58
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
View File

@ -28,49 +28,6 @@
#include "dm_helpers.h"
#include "amdgpu_dm.h"
static bool link_get_psr_caps(struct dc_link *link)
{
uint8_t psr_dpcd_data[EDP_PSR_RECEIVER_CAP_SIZE];
uint8_t edp_rev_dpcd_data;
if (!dm_helpers_dp_read_dpcd(NULL, link, DP_PSR_SUPPORT,
psr_dpcd_data, sizeof(psr_dpcd_data)))
return false;
if (!dm_helpers_dp_read_dpcd(NULL, link, DP_EDP_DPCD_REV,
&edp_rev_dpcd_data, sizeof(edp_rev_dpcd_data)))
return false;
link->dpcd_caps.psr_caps.psr_version = psr_dpcd_data[0];
link->dpcd_caps.psr_caps.edp_revision = edp_rev_dpcd_data;
#ifdef CONFIG_DRM_AMD_DC_DCN
if (link->dpcd_caps.psr_caps.psr_version > 0x1) {
uint8_t alpm_dpcd_data;
uint8_t su_granularity_dpcd_data;
if (!dm_helpers_dp_read_dpcd(NULL, link, DP_RECEIVER_ALPM_CAP,
&alpm_dpcd_data, sizeof(alpm_dpcd_data)))
return false;
if (!dm_helpers_dp_read_dpcd(NULL, link, DP_PSR2_SU_Y_GRANULARITY,
&su_granularity_dpcd_data, sizeof(su_granularity_dpcd_data)))
return false;
link->dpcd_caps.psr_caps.y_coordinate_required = psr_dpcd_data[1] & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
link->dpcd_caps.psr_caps.su_granularity_required = psr_dpcd_data[1] & DP_PSR2_SU_GRANULARITY_REQUIRED;
link->dpcd_caps.psr_caps.alpm_cap = alpm_dpcd_data & DP_ALPM_CAP;
link->dpcd_caps.psr_caps.standby_support = alpm_dpcd_data & (1 << 1);
link->dpcd_caps.psr_caps.su_y_granularity = su_granularity_dpcd_data;
}
#endif
return true;
}
#ifdef CONFIG_DRM_AMD_DC_DCN
static bool link_supports_psrsu(struct dc_link *link)
{
@ -82,12 +39,12 @@ static bool link_supports_psrsu(struct dc_link *link)
if (dc->ctx->dce_version < DCN_VERSION_3_1)
return false;
if (!link->dpcd_caps.psr_caps.alpm_cap ||
!link->dpcd_caps.psr_caps.y_coordinate_required)
if (!link->dpcd_caps.alpm_caps.bits.AUX_WAKE_ALPM_CAP ||
!link->dpcd_caps.psr_info.psr_dpcd_caps.bits.Y_COORDINATE_REQUIRED)
return false;
if (link->dpcd_caps.psr_caps.su_granularity_required &&
!link->dpcd_caps.psr_caps.su_y_granularity)
if (link->dpcd_caps.psr_info.psr_dpcd_caps.bits.SU_GRANULARITY_REQUIRED &&
!link->dpcd_caps.psr_info.psr2_su_y_granularity_cap)
return false;
return true;
@ -107,12 +64,7 @@ void amdgpu_dm_set_psr_caps(struct dc_link *link)
if (link->type == dc_connection_none)
return;
if (!link_get_psr_caps(link)) {
DRM_ERROR("amdgpu: Failed to read PSR Caps!\n");
return;
}
if (link->dpcd_caps.psr_caps.psr_version == 0) {
if (link->dpcd_caps.psr_info.psr_version == 0) {
link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
link->psr_settings.psr_feature_enabled = false;

1
drivers/gpu/drm/amd/display/dc/Makefile
View File

@ -36,6 +36,7 @@ DC_LIBS += dcn301
DC_LIBS += dcn302
DC_LIBS += dcn303
DC_LIBS += dcn31
DC_LIBS += dcn315
DC_LIBS += dcn316
endif

1
drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
View File

@ -76,6 +76,7 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
case DCN_VERSION_3_02:
case DCN_VERSION_3_03:
case DCN_VERSION_3_1:
case DCN_VERSION_3_15:
case DCN_VERSION_3_16:
*h = dal_cmd_tbl_helper_dce112_get_table2();
return true;

9
drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
View File

@ -154,6 +154,15 @@ AMD_DAL_CLK_MGR_DCN31 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn31/,$(CLK_MGR_DC
AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN31)
###############################################################################
# DCN315
###############################################################################
CLK_MGR_DCN315 = dcn315_smu.o dcn315_clk_mgr.o
AMD_DAL_CLK_MGR_DCN315 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn315/,$(CLK_MGR_DCN315))
AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN315)
###############################################################################
# DCN316
###############################################################################

23
drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
View File

@ -43,6 +43,7 @@
#include "dcn30/dcn30_clk_mgr.h"
#include "dcn301/vg_clk_mgr.h"
#include "dcn31/dcn31_clk_mgr.h"
#include "dcn315/dcn315_clk_mgr.h"
#include "dcn316/dcn316_clk_mgr.h"
@ -290,6 +291,19 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
dcn31_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
return &clk_mgr->base.base;
}
break;
case AMDGPU_FAMILY_GC_10_3_6: {
struct clk_mgr_dcn315 *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
if (clk_mgr == NULL) {
BREAK_TO_DEBUGGER();
return NULL;
}
dcn315_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
return &clk_mgr->base.base;
}
break;
case AMDGPU_FAMILY_GC_10_3_7: {
struct clk_mgr_dcn316 *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
@ -301,6 +315,7 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
dcn316_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
return &clk_mgr->base.base;
}
break;
#endif
default:
@ -334,11 +349,15 @@ void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base)
break;
case FAMILY_YELLOW_CARP:
dcn31_clk_mgr_destroy(clk_mgr);
dcn31_clk_mgr_destroy(clk_mgr);
break;
case AMDGPU_FAMILY_GC_10_3_6:
dcn315_clk_mgr_destroy(clk_mgr);
break;
case AMDGPU_FAMILY_GC_10_3_7:
dcn316_clk_mgr_destroy(clk_mgr);
dcn316_clk_mgr_destroy(clk_mgr);
break;
default:

2
drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
View File

@ -374,6 +374,8 @@ void dce_clock_read_ss_info(struct clk_mgr_internal *clk_mgr_dce)
clk_mgr_dce->dprefclk_ss_percentage =
info.spread_spectrum_percentage;
}
if (clk_mgr_dce->base.ctx->dc->debug.ignore_dpref_ss)
clk_mgr_dce->dprefclk_ss_percentage = 0;
}
}
}

3
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
View File

@ -101,7 +101,8 @@ static uint32_t rv1_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsi
return res_val;
}
int rv1_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, unsigned int msg_id, unsigned int param)
static int rv1_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,
unsigned int msg_id, unsigned int param)
{
uint32_t result;

2
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
View File

@ -697,6 +697,8 @@ void dcn31_clk_mgr_construct(
clk_mgr->base.base.dprefclk_khz = 600000;
clk_mgr->base.dccg->ref_dtbclk_khz = 600000;
dce_clock_read_ss_info(&clk_mgr->base);
/*if bios enabled SS, driver needs to adjust dtb clock, only enable with correct bios*/
//clk_mgr->base.dccg->ref_dtbclk_khz = dce_adjust_dp_ref_freq_for_ss(clk_mgr_internal, clk_mgr->base.base.dprefclk_khz);
clk_mgr->base.base.bw_params = &dcn31_bw_params;

617
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c Normal file
View File

@ -0,0 +1,617 @@
/*
* Copyright 2021 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dccg.h"
#include "clk_mgr_internal.h"
// For dce12_get_dp_ref_freq_khz
#include "dce100/dce_clk_mgr.h"
// For dcn20_update_clocks_update_dpp_dto
#include "dcn20/dcn20_clk_mgr.h"
#include "dcn31/dcn31_clk_mgr.h"
#include "dcn315_clk_mgr.h"
#include "core_types.h"
#include "dcn315_smu.h"
#include "dm_helpers.h"
#include "dc_dmub_srv.h"
#if defined (CONFIG_DRM_AMD_DC_DP2_0)
#include "dc_link_dp.h"
#endif
#define TO_CLK_MGR_DCN315(clk_mgr)\
container_of(clk_mgr, struct clk_mgr_dcn315, base)
static int dcn315_get_active_display_cnt_wa(
struct dc *dc,
struct dc_state *context)
{
int i, display_count;
bool tmds_present = false;
display_count = 0;
for (i = 0; i < context->stream_count; i++) {
const struct dc_stream_state *stream = context->streams[i];
if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
tmds_present = true;
}
for (i = 0; i < dc->link_count; i++) {
const struct dc_link *link = dc->links[i];
/* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
if (link->link_enc && link->link_enc->funcs->is_dig_enabled &&
link->link_enc->funcs->is_dig_enabled(link->link_enc))
display_count++;
}
/* WA for hang on HDMI after display off back back on*/
if (display_count == 0 && tmds_present)
display_count = 1;
return display_count;
}
static void dcn315_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)
{
struct dc *dc = clk_mgr_base->ctx->dc;
int i;
for (i = 0; i < dc->res_pool->pipe_count; ++i) {
struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
if (pipe->top_pipe || pipe->prev_odm_pipe)
continue;
if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))) {
if (disable)
pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
else
pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
}
}
}
static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base,
struct dc_state *context,
bool safe_to_lower)
{
union dmub_rb_cmd cmd;
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
struct dc *dc = clk_mgr_base->ctx->dc;
int display_count;
bool update_dppclk = false;
bool update_dispclk = false;
bool dpp_clock_lowered = false;
if (dc->work_arounds.skip_clock_update)
return;
clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
/*
* if it is safe to lower, but we are already in the lower state, we don't have to do anything
* also if safe to lower is false, we just go in the higher state
*/
clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
if (safe_to_lower) {
/* check that we're not already in lower */
if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
display_count = dcn315_get_active_display_cnt_wa(dc, context);
/* if we can go lower, go lower */
if (display_count == 0) {
union display_idle_optimization_u idle_info = { 0 };
idle_info.idle_info.df_request_disabled = 1;
idle_info.idle_info.phy_ref_clk_off = 1;
dcn315_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
/* update power state */
clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
}
}
} else {
/* check that we're not already in D0 */
if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
union display_idle_optimization_u idle_info = { 0 };
dcn315_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
/* update power state */
clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
}
}
if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
dcn315_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
}
if (should_set_clock(safe_to_lower,
new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
dcn315_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
}
// workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
if (new_clocks->dppclk_khz < 100000)
new_clocks->dppclk_khz = 100000;
if (new_clocks->dispclk_khz < 100000)
new_clocks->dispclk_khz = 100000;
}
if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
dpp_clock_lowered = true;
clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
update_dppclk = true;
}
if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
dcn315_disable_otg_wa(clk_mgr_base, true);
clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
dcn315_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
dcn315_disable_otg_wa(clk_mgr_base, false);
update_dispclk = true;
}
if (dpp_clock_lowered) {
// increase per DPP DTO before lowering global dppclk
dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
dcn315_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
} else {
// increase global DPPCLK before lowering per DPP DTO
if (update_dppclk || update_dispclk)
dcn315_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
// always update dtos unless clock is lowered and not safe to lower
if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
}
// notify DMCUB of latest clocks
memset(&cmd, 0, sizeof(cmd));
cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR;
cmd.notify_clocks.header.sub_type = DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS;
cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz;
cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz =
clk_mgr_base->clks.dcfclk_deep_sleep_khz;
cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz;
cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz;
dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
}
static void dcn315_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
{
return;
}
static struct clk_bw_params dcn315_bw_params = {
.vram_type = Ddr4MemType,
.num_channels = 1,
.clk_table = {
.num_entries = 5,
},
};
static struct wm_table ddr5_wm_table = {
.entries = {
{
.wm_inst = WM_A,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 64.0,
.sr_exit_time_us = 11.5,
.sr_enter_plus_exit_time_us = 14.5,
.valid = true,
},
{
.wm_inst = WM_B,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 64.0,
.sr_exit_time_us = 11.5,
.sr_enter_plus_exit_time_us = 14.5,
.valid = true,
},
{
.wm_inst = WM_C,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 64.0,
.sr_exit_time_us = 11.5,
.sr_enter_plus_exit_time_us = 14.5,
.valid = true,
},
{
.wm_inst = WM_D,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 64.0,
.sr_exit_time_us = 11.5,
.sr_enter_plus_exit_time_us = 14.5,
.valid = true,
},
}
};
static struct wm_table lpddr5_wm_table = {
.entries = {
{
.wm_inst = WM_A,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.65333,
.sr_exit_time_us = 11.5,
.sr_enter_plus_exit_time_us = 14.5,
.valid = true,
},
{
.wm_inst = WM_B,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.65333,
.sr_exit_time_us = 11.5,
.sr_enter_plus_exit_time_us = 14.5,
.valid = true,
},
{
.wm_inst = WM_C,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.65333,
.sr_exit_time_us = 11.5,
.sr_enter_plus_exit_time_us = 14.5,
.valid = true,
},
{
.wm_inst = WM_D,
.wm_type = WM_TYPE_PSTATE_CHG,
.pstate_latency_us = 11.65333,
.sr_exit_time_us = 11.5,
.sr_enter_plus_exit_time_us = 14.5,
.valid = true,
},
}
};
static DpmClocks_315_t dummy_clocks;
static struct dcn315_watermarks dummy_wms = { 0 };
static void dcn315_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn315_watermarks *table)
{
int i, num_valid_sets;
num_valid_sets = 0;
for (i = 0; i < WM_SET_COUNT; i++) {
/* skip empty entries, the smu array has no holes*/
if (!bw_params->wm_table.entries[i].valid)
continue;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
/* We will not select WM based on fclk, so leave it as unconstrained */
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
if (i == 0)
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
else {
/* add 1 to make it non-overlapping with next lvl */
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
}
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
bw_params->clk_table.entries[i].dcfclk_mhz;
} else {
/* unconstrained for memory retraining */
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
/* Modify previous watermark range to cover up to max */
table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
}
num_valid_sets++;
}
ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
/* modify the min and max to make sure we cover the whole range*/
table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;
table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;
table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;
table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
/* This is for writeback only, does not matter currently as no writeback support*/
table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;
table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;
table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;
table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;
}
static void dcn315_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
{
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
struct clk_mgr_dcn315 *clk_mgr_dcn315 = TO_CLK_MGR_DCN315(clk_mgr);
struct dcn315_watermarks *table = clk_mgr_dcn315->smu_wm_set.wm_set;
if (!clk_mgr->smu_ver)
return;
if (!table || clk_mgr_dcn315->smu_wm_set.mc_address.quad_part == 0)
return;
memset(table, 0, sizeof(*table));
dcn315_build_watermark_ranges(clk_mgr_base->bw_params, table);
dcn315_smu_set_dram_addr_high(clk_mgr,
clk_mgr_dcn315->smu_wm_set.mc_address.high_part);
dcn315_smu_set_dram_addr_low(clk_mgr,
clk_mgr_dcn315->smu_wm_set.mc_address.low_part);
dcn315_smu_transfer_wm_table_dram_2_smu(clk_mgr);
}
static void dcn315_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
struct dcn315_smu_dpm_clks *smu_dpm_clks)
{
DpmClocks_315_t *table = smu_dpm_clks->dpm_clks;
if (!clk_mgr->smu_ver)
return;
if (!table || smu_dpm_clks->mc_address.quad_part == 0)
return;
memset(table, 0, sizeof(*table));
dcn315_smu_set_dram_addr_high(clk_mgr,
smu_dpm_clks->mc_address.high_part);
dcn315_smu_set_dram_addr_low(clk_mgr,
smu_dpm_clks->mc_address.low_part);
dcn315_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
}
static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks)
{
uint32_t max = 0;
int i;
for (i = 0; i < num_clocks; ++i) {
if (clocks[i] > max)
max = clocks[i];
}
return max;
}
static unsigned int find_clk_for_voltage(
const DpmClocks_315_t *clock_table,
const uint32_t clocks[],
unsigned int voltage)
{
int i;
for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++) {
if (clock_table->SocVoltage[i] == voltage)
return clocks[i];
}
ASSERT(0);
return 0;
}
static void dcn315_clk_mgr_helper_populate_bw_params(
struct clk_mgr_internal *clk_mgr,
struct integrated_info *bios_info,
const DpmClocks_315_t *clock_table)
{
int i, j;
struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
uint32_t max_dispclk = 0, max_dppclk = 0;
j = -1;
ASSERT(NUM_DF_PSTATE_LEVELS <= MAX_NUM_DPM_LVL);
/* Find lowest DPM, FCLK is filled in reverse order*/
for (i = NUM_DF_PSTATE_LEVELS - 1; i >= 0; i--) {
if (clock_table->DfPstateTable[i].FClk != 0) {
j = i;
break;
}
}
if (j == -1) {
/* clock table is all 0s, just use our own hardcode */
ASSERT(0);
return;
}
bw_params->clk_table.num_entries = j + 1;
/* dispclk and dppclk can be max at any voltage, same number of levels for both */
if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS &&
clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) {
max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled);
max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled);
} else {
ASSERT(0);
}
for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
int temp;
bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk;
bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk;
bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].Voltage;
bw_params->clk_table.entries[i].wck_ratio = 1;
temp = find_clk_for_voltage(clock_table, clock_table->DcfClocks, clock_table->DfPstateTable[j].Voltage);
if (temp)
bw_params->clk_table.entries[i].dcfclk_mhz = temp;
temp = find_clk_for_voltage(clock_table, clock_table->SocClocks, clock_table->DfPstateTable[j].Voltage);
if (temp)
bw_params->clk_table.entries[i].socclk_mhz = temp;
bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
}
bw_params->vram_type = bios_info->memory_type;
bw_params->num_channels = bios_info->ma_channel_number;
for (i = 0; i < WM_SET_COUNT; i++) {
bw_params->wm_table.entries[i].wm_inst = i;
if (i >= bw_params->clk_table.num_entries) {
bw_params->wm_table.entries[i].valid = false;
continue;
}
bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
bw_params->wm_table.entries[i].valid = true;
}
}
static void dcn315_enable_pme_wa(struct clk_mgr *clk_mgr_base)
{
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
dcn315_smu_enable_pme_wa(clk_mgr);
}
static struct clk_mgr_funcs dcn315_funcs = {
.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
.update_clocks = dcn315_update_clocks,
.init_clocks = dcn31_init_clocks,
.enable_pme_wa = dcn315_enable_pme_wa,
.are_clock_states_equal = dcn31_are_clock_states_equal,
.notify_wm_ranges = dcn315_notify_wm_ranges
};
extern struct clk_mgr_funcs dcn3_fpga_funcs;
void dcn315_clk_mgr_construct(
struct dc_context *ctx,
struct clk_mgr_dcn315 *clk_mgr,
struct pp_smu_funcs *pp_smu,
struct dccg *dccg)
{
struct dcn315_smu_dpm_clks smu_dpm_clks = { 0 };
clk_mgr->base.base.ctx = ctx;
clk_mgr->base.base.funcs = &dcn315_funcs;
clk_mgr->base.pp_smu = pp_smu;
clk_mgr->base.dccg = dccg;
clk_mgr->base.dfs_bypass_disp_clk = 0;
clk_mgr->base.dprefclk_ss_percentage = 0;
clk_mgr->base.dprefclk_ss_divider = 1000;
clk_mgr->base.ss_on_dprefclk = false;
clk_mgr->base.dfs_ref_freq_khz = 48000;
clk_mgr->smu_wm_set.wm_set = (struct dcn315_watermarks *)dm_helpers_allocate_gpu_mem(
clk_mgr->base.base.ctx,
DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
sizeof(struct dcn315_watermarks),
&clk_mgr->smu_wm_set.mc_address.quad_part);
if (!clk_mgr->smu_wm_set.wm_set) {
clk_mgr->smu_wm_set.wm_set = &dummy_wms;
clk_mgr->smu_wm_set.mc_address.quad_part = 0;
}
ASSERT(clk_mgr->smu_wm_set.wm_set);
smu_dpm_clks.dpm_clks = (DpmClocks_315_t *)dm_helpers_allocate_gpu_mem(
clk_mgr->base.base.ctx,
DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
sizeof(DpmClocks_315_t),
&smu_dpm_clks.mc_address.quad_part);
if (smu_dpm_clks.dpm_clks == NULL) {
smu_dpm_clks.dpm_clks = &dummy_clocks;
smu_dpm_clks.mc_address.quad_part = 0;
}
ASSERT(smu_dpm_clks.dpm_clks);
if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
clk_mgr->base.base.funcs = &dcn3_fpga_funcs;
} else {
struct clk_log_info log_info = {0};
clk_mgr->base.smu_ver = dcn315_smu_get_smu_version(&clk_mgr->base);
if (clk_mgr->base.smu_ver > 0)
clk_mgr->base.smu_present = true;
if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
dcn315_bw_params.wm_table = lpddr5_wm_table;
} else {
dcn315_bw_params.wm_table = ddr5_wm_table;
}
/* Saved clocks configured at boot for debug purposes */
dcn315_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info);
}
clk_mgr->base.base.dprefclk_khz = 600000;
clk_mgr->base.dccg->ref_dtbclk_khz = 600000;
dce_clock_read_ss_info(&clk_mgr->base);
clk_mgr->base.base.bw_params = &dcn315_bw_params;
if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {
dcn315_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
if (ctx->dc_bios && ctx->dc_bios->integrated_info) {
dcn315_clk_mgr_helper_populate_bw_params(
&clk_mgr->base,
ctx->dc_bios->integrated_info,
smu_dpm_clks.dpm_clks);
}
}
if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
smu_dpm_clks.dpm_clks);
}
void dcn315_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)
{
struct clk_mgr_dcn315 *clk_mgr = TO_CLK_MGR_DCN315(clk_mgr_int);
if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)
dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
clk_mgr->smu_wm_set.wm_set);
}

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/*
* Copyright 2021 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DCN315_CLK_MGR_H__
#define __DCN315_CLK_MGR_H__
#include "clk_mgr_internal.h"
struct dcn315_watermarks;
struct dcn315_smu_watermark_set {
struct dcn315_watermarks *wm_set;
union large_integer mc_address;
};
struct clk_mgr_dcn315 {
struct clk_mgr_internal base;
struct dcn315_smu_watermark_set smu_wm_set;
};
void dcn315_clk_mgr_construct(struct dc_context *ctx,
struct clk_mgr_dcn315 *clk_mgr,
struct pp_smu_funcs *pp_smu,
struct dccg *dccg);
void dcn315_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int);
#endif //__DCN315_CLK_MGR_H__

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drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c Normal file
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/*
* Copyright 2021 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "core_types.h"
#include "clk_mgr_internal.h"
#include "reg_helper.h"
#include "dm_helpers.h"
#include "dcn315_smu.h"
#include "mp/mp_13_0_5_offset.h"
#define MAX_INSTANCE 6
#define MAX_SEGMENT 6
struct IP_BASE_INSTANCE
{
unsigned int segment[MAX_SEGMENT];
};
struct IP_BASE
{
struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
};
static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00, 0 } },
{ { 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0 } } } };
static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },
{ { 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0 } } } };
#define regBIF_BX_PF2_RSMU_INDEX 0x0000
#define regBIF_BX_PF2_RSMU_INDEX_BASE_IDX 1
#define regBIF_BX_PF2_RSMU_DATA 0x0001
#define regBIF_BX_PF2_RSMU_DATA_BASE_IDX 1
#define REG(reg_name) \
(MP0_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
#define FN(reg_name, field) \
FD(reg_name##__##field)
#define REG_NBIO(reg_name) \
(NBIO_BASE.instance[0].segment[regBIF_BX_PF2_ ## reg_name ## _BASE_IDX] + regBIF_BX_PF2_ ## reg_name)
#define mmMP1_C2PMSG_3 0x3B1050C
#define VBIOSSMC_MSG_TestMessage 0x01 ///< To check if PMFW is alive and responding. Requirement specified by PMFW team
#define VBIOSSMC_MSG_GetPmfwVersion 0x02 ///< Get PMFW version
#define VBIOSSMC_MSG_Spare0 0x03 ///< Spare0
#define VBIOSSMC_MSG_SetDispclkFreq 0x04 ///< Set display clock frequency in MHZ
#define VBIOSSMC_MSG_Spare1 0x05 ///< Spare1
#define VBIOSSMC_MSG_SetDppclkFreq 0x06 ///< Set DPP clock frequency in MHZ
#define VBIOSSMC_MSG_SetHardMinDcfclkByFreq 0x07 ///< Set DCF clock frequency hard min in MHZ
#define VBIOSSMC_MSG_SetMinDeepSleepDcfclk 0x08 ///< Set DCF clock minimum frequency in deep sleep in MHZ
#define VBIOSSMC_MSG_SetPhyclkVoltageByFreq 0x09 ///< Set display phy clock frequency in MHZ in case VMIN does not support phy frequency
#define VBIOSSMC_MSG_GetFclkFrequency 0x0A ///< Get FCLK frequency, return frequemcy in MHZ
#define VBIOSSMC_MSG_SetDisplayCount 0x0B ///< Inform PMFW of number of display connected
#define VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown 0x0C ///< To ask PMFW turn off TMDP 48MHz refclk during display off to save power
#define VBIOSSMC_MSG_UpdatePmeRestore 0x0D ///< To ask PMFW to write into Azalia for PME wake up event
#define VBIOSSMC_MSG_SetVbiosDramAddrHigh 0x0E ///< Set DRAM address high 32 bits for WM table transfer
#define VBIOSSMC_MSG_SetVbiosDramAddrLow 0x0F ///< Set DRAM address low 32 bits for WM table transfer
#define VBIOSSMC_MSG_TransferTableSmu2Dram 0x10 ///< Transfer table from PMFW SRAM to system DRAM
#define VBIOSSMC_MSG_TransferTableDram2Smu 0x11 ///< Transfer table from system DRAM to PMFW
#define VBIOSSMC_MSG_SetDisplayIdleOptimizations 0x12 ///< Set Idle state optimization for display off
#define VBIOSSMC_MSG_GetDprefclkFreq 0x13 ///< Get DPREF clock frequency. Return in MHZ
#define VBIOSSMC_Message_Count 0x14 ///< Total number of VBIS and DAL messages
#define VBIOSSMC_Status_BUSY 0x0
#define VBIOSSMC_Result_OK 0x01 ///< Message Response OK
#define VBIOSSMC_Result_Failed 0xFF ///< Message Response Failed
#define VBIOSSMC_Result_UnknownCmd 0xFE ///< Message Response Unknown Command
#define VBIOSSMC_Result_CmdRejectedPrereq 0xFD ///< Message Response Command Failed Prerequisite
#define VBIOSSMC_Result_CmdRejectedBusy 0xFC ///< Message Response Command Rejected due to PMFW is busy. Sender should retry sending this message
/*
* Function to be used instead of REG_WAIT macro because the wait ends when
* the register is NOT EQUAL to zero, and because the translation in msg_if.h
* won't work with REG_WAIT.
*/
static uint32_t dcn315_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)
{
uint32_t res_val = VBIOSSMC_Status_BUSY;
do {
res_val = REG_READ(MP1_SMN_C2PMSG_38);
if (res_val != VBIOSSMC_Status_BUSY)
break;
if (delay_us >= 1000)
msleep(delay_us/1000);
else if (delay_us > 0)
udelay(delay_us);
} while (max_retries--);
return res_val;
}
static int dcn315_smu_send_msg_with_param(
struct clk_mgr_internal *clk_mgr,
unsigned int msg_id, unsigned int param)
{
uint32_t result;
result = dcn315_smu_wait_for_response(clk_mgr, 10, 200000);
ASSERT(result == VBIOSSMC_Result_OK);
if (result == VBIOSSMC_Status_BUSY) {
return -1;
}
/* First clear response register */
REG_WRITE(MP1_SMN_C2PMSG_38, VBIOSSMC_Status_BUSY);
/* Set the parameter register for the SMU message, unit is Mhz */
REG_WRITE(MP1_SMN_C2PMSG_37, param);
/* Trigger the message transaction by writing the message ID */
generic_write_indirect_reg(CTX,
REG_NBIO(RSMU_INDEX), REG_NBIO(RSMU_DATA),
mmMP1_C2PMSG_3, msg_id);
result = dcn315_smu_wait_for_response(clk_mgr, 10, 200000);
if (result == VBIOSSMC_Status_BUSY) {
ASSERT(0);
dm_helpers_smu_timeout(CTX, msg_id, param, 10 * 200000);
}
return REG_READ(MP1_SMN_C2PMSG_37);
}
int dcn315_smu_get_smu_version(struct clk_mgr_internal *clk_mgr)
{
return dcn315_smu_send_msg_with_param(
clk_mgr,
VBIOSSMC_MSG_GetPmfwVersion,
0);
}
int dcn315_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)
{
int actual_dispclk_set_mhz = -1;
if (!clk_mgr->smu_present)
return requested_dispclk_khz;
/* Unit of SMU msg parameter is Mhz */
actual_dispclk_set_mhz = dcn315_smu_send_msg_with_param(
clk_mgr,
VBIOSSMC_MSG_SetDispclkFreq,
khz_to_mhz_ceil(requested_dispclk_khz));
return actual_dispclk_set_mhz * 1000;
}
int dcn315_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz)
{
int actual_dcfclk_set_mhz = -1;
if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)
return -1;
if (!clk_mgr->smu_present)
return requested_dcfclk_khz;
actual_dcfclk_set_mhz = dcn315_smu_send_msg_with_param(
clk_mgr,
VBIOSSMC_MSG_SetHardMinDcfclkByFreq,
khz_to_mhz_ceil(requested_dcfclk_khz));
return actual_dcfclk_set_mhz * 1000;
}
int dcn315_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz)
{
int actual_min_ds_dcfclk_mhz = -1;
if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)
return -1;
if (!clk_mgr->smu_present)
return requested_min_ds_dcfclk_khz;
actual_min_ds_dcfclk_mhz = dcn315_smu_send_msg_with_param(
clk_mgr,
VBIOSSMC_MSG_SetMinDeepSleepDcfclk,
khz_to_mhz_ceil(requested_min_ds_dcfclk_khz));
return actual_min_ds_dcfclk_mhz * 1000;
}
int dcn315_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)
{
int actual_dppclk_set_mhz = -1;
if (!clk_mgr->smu_present)
return requested_dpp_khz;
actual_dppclk_set_mhz = dcn315_smu_send_msg_with_param(
clk_mgr,
VBIOSSMC_MSG_SetDppclkFreq,
khz_to_mhz_ceil(requested_dpp_khz));
return actual_dppclk_set_mhz * 1000;
}
void dcn315_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info)
{
if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)
return;
if (!clk_mgr->smu_present)
return;
//TODO: Work with smu team to define optimization options.
dcn315_smu_send_msg_with_param(
clk_mgr,
VBIOSSMC_MSG_SetDisplayIdleOptimizations,
idle_info);
}
void dcn315_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)
{
union display_idle_optimization_u idle_info = { 0 };
if (!clk_mgr->smu_present)
return;
if (enable) {
idle_info.idle_info.df_request_disabled = 1;
idle_info.idle_info.phy_ref_clk_off = 1;
}
dcn315_smu_send_msg_with_param(
clk_mgr,
VBIOSSMC_MSG_SetDisplayIdleOptimizations,
idle_info.data);
}
void dcn315_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)
{
if (!clk_mgr->smu_present)
return;
dcn315_smu_send_msg_with_param(
clk_mgr,
VBIOSSMC_MSG_UpdatePmeRestore,
0);
}
void dcn315_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)
{
if (!clk_mgr->smu_present)
return;
dcn315_smu_send_msg_with_param(clk_mgr,
VBIOSSMC_MSG_SetVbiosDramAddrHigh, addr_high);
}
void dcn315_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)
{
if (!clk_mgr->smu_present)
return;
dcn315_smu_send_msg_with_param(clk_mgr,
VBIOSSMC_MSG_SetVbiosDramAddrLow, addr_low);
}
void dcn315_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr)
{
if (!clk_mgr->smu_present)
return;
dcn315_smu_send_msg_with_param(clk_mgr,
VBIOSSMC_MSG_TransferTableSmu2Dram, TABLE_DPMCLOCKS);
}
void dcn315_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)
{
if (!clk_mgr->smu_present)
return;
dcn315_smu_send_msg_with_param(clk_mgr,
VBIOSSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS);
}

126
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h Normal file
View File

@ -0,0 +1,126 @@
/*
* Copyright 2021 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef DAL_DC_315_SMU_H_
#define DAL_DC_315_SMU_H_
#include "os_types.h"
#define PMFW_DRIVER_IF_VERSION 4
#define NUM_DCFCLK_DPM_LEVELS 4
#define NUM_DISPCLK_DPM_LEVELS 4
#define NUM_DPPCLK_DPM_LEVELS 4
#define NUM_SOCCLK_DPM_LEVELS 4
#define NUM_VCN_DPM_LEVELS 4
#define NUM_SOC_VOLTAGE_LEVELS 4
#define NUM_DF_PSTATE_LEVELS 4
typedef struct {
uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
uint16_t MinMclk;
uint16_t MaxMclk;
uint8_t WmSetting;
uint8_t WmType; // Used for normal pstate change or memory retraining
uint8_t Padding[2];
} WatermarkRowGeneric_t;
#define NUM_WM_RANGES 4
#define WM_PSTATE_CHG 0
#define WM_RETRAINING 1
typedef enum {
WM_SOCCLK = 0,
WM_DCFCLK,
WM_COUNT,
} WM_CLOCK_e;
typedef struct {
uint32_t FClk;
uint32_t MemClk;
uint32_t Voltage;
} DfPstateTable_t;
//Freq in MHz
//Voltage in milli volts with 2 fractional bits
typedef struct {
uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];
uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
uint32_t VClocks[NUM_VCN_DPM_LEVELS];
uint32_t DClocks[NUM_VCN_DPM_LEVELS];
uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];
DfPstateTable_t DfPstateTable[NUM_DF_PSTATE_LEVELS];
uint8_t NumDcfClkLevelsEnabled;
uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk
uint8_t NumSocClkLevelsEnabled;
uint8_t VcnClkLevelsEnabled; //Applies to both Vclk and Dclk
uint8_t NumDfPstatesEnabled;
uint8_t spare[3];
uint32_t MinGfxClk;
uint32_t MaxGfxClk;
} DpmClocks_315_t;
struct dcn315_watermarks {
// Watermarks
WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
uint32_t MmHubPadding[7]; // SMU internal use
};
struct dcn315_smu_dpm_clks {
DpmClocks_315_t *dpm_clks;
union large_integer mc_address;
};
#define TABLE_WATERMARKS 1 // Called by DAL through VBIOS
#define TABLE_DPMCLOCKS 4 // Called by Driver and VBIOS
struct display_idle_optimization {
unsigned int df_request_disabled : 1;
unsigned int phy_ref_clk_off : 1;
unsigned int s0i2_rdy : 1;
unsigned int reserved : 29;
};
union display_idle_optimization_u {
struct display_idle_optimization idle_info;
uint32_t data;
};
int dcn315_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
int dcn315_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
int dcn315_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
int dcn315_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz);
int dcn315_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
void dcn315_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
void dcn315_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
void dcn315_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
void dcn315_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);
void dcn315_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);
void dcn315_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
void dcn315_smu_request_voltage_via_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz);
void dcn315_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
#endif /* DAL_DC_315_SMU_H_ */

13
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
View File

@ -485,7 +485,7 @@ static unsigned int find_clk_for_voltage(
return clock;
}
void dcn316_clk_mgr_helper_populate_bw_params(
static void dcn316_clk_mgr_helper_populate_bw_params(
struct clk_mgr_internal *clk_mgr,
struct integrated_info *bios_info,
const DpmClocks_316_t *clock_table)
@ -530,7 +530,16 @@ void dcn316_clk_mgr_helper_populate_bw_params(
bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk;
bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk;
bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].Voltage;
bw_params->clk_table.entries[i].wck_ratio = 1;
switch (clock_table->DfPstateTable[j].WckRatio) {
case WCK_RATIO_1_2:
bw_params->clk_table.entries[i].wck_ratio = 2;
break;
case WCK_RATIO_1_4:
bw_params->clk_table.entries[i].wck_ratio = 4;
break;
default:
bw_params->clk_table.entries[i].wck_ratio = 1;
}
temp = find_clk_for_voltage(clock_table, clock_table->DcfClocks, clock_table->DfPstateTable[j].Voltage);
if (temp)
bw_params->clk_table.entries[i].dcfclk_mhz = temp;

18
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c
View File

@ -111,7 +111,7 @@ static uint32_t dcn316_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, u
return res_val;
}
int dcn316_smu_send_msg_with_param(
static int dcn316_smu_send_msg_with_param(
struct clk_mgr_internal *clk_mgr,
unsigned int msg_id, unsigned int param)
{
@ -168,22 +168,6 @@ int dcn316_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispc
return actual_dispclk_set_mhz * 1000;
}
int dcn316_smu_set_voltage_via_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz)
{
int actual_phypclk_set_mhz = -1;
if (!clk_mgr->smu_present && requested_phyclk_khz)
return requested_phyclk_khz;
/* Unit of SMU msg parameter is Mhz */
actual_phypclk_set_mhz = dcn316_smu_send_msg_with_param(
clk_mgr,
VBIOSSMC_MSG_SetPhyclkVoltageByFreq,
khz_to_mhz_ceil(requested_phyclk_khz));
return actual_phypclk_set_mhz * 1000;
}
int dcn316_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz)
{
int actual_dcfclk_set_mhz = -1;

9
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h
View File

@ -57,10 +57,19 @@ typedef enum {
WM_COUNT,
} WM_CLOCK_e;
typedef enum{
WCK_RATIO_1_1 = 0, // DDR5, Wck:ck is always 1:1;
WCK_RATIO_1_2,
WCK_RATIO_1_4,
WCK_RATIO_MAX
} WCK_RATIO_e;
typedef struct {
uint32_t FClk;
uint32_t MemClk;
uint32_t Voltage;
uint8_t WckRatio;
uint8_t Spare[3];
} DfPstateTable_t;
//Freq in MHz

6
drivers/gpu/drm/amd/display/dc/core/dc.c
View File

@ -3737,8 +3737,8 @@ bool dc_is_dmub_outbox_supported(struct dc *dc)
return dc->debug.enable_dmub_aux_for_legacy_ddc;
}
/**
* dc_process_dmub_aux_transfer_async - Submits aux command to dmub via inbox message
/*
*****************************************************************************
* Function: dc_enable_dmub_notifications
*
* @brief
@ -3780,7 +3780,7 @@ void dc_enable_dmub_outbox(struct dc *dc)
}
/**
*****************************************************************************
* dc_process_dmub_aux_transfer_async - Submits aux command to dmub via inbox message
* Sets port index appropriately for legacy DDC
* @dc: dc structure
* @link_index: link index

35
drivers/gpu/drm/amd/display/dc/core/dc_link.c
View File

@ -1197,6 +1197,22 @@ static bool detect_link_and_local_sink(struct dc_link *link,
return false;
}
if (link->type == dc_connection_sst_branch &&
link->dpcd_caps.dongle_type ==
DISPLAY_DONGLE_DP_VGA_CONVERTER &&
reason == DETECT_REASON_HPDRX) {
/* Abort detection for DP-VGA adapters when EDID
* can't be read and detection reason is VGA-side
* hotplug
*/
if (prev_sink)
dc_sink_release(prev_sink);
link_disconnect_sink(link);
return true;
}
break;
default:
break;
@ -1289,7 +1305,7 @@ static bool detect_link_and_local_sink(struct dc_link *link,
*/
link->dongle_max_pix_clk = 0;
dc_link_dp_clear_rx_status(link);
dc_link_clear_dprx_states(link);
}
LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p edid same=%d\n",
@ -1970,7 +1986,7 @@ static enum dc_status enable_link_dp(struct dc_state *state,
msleep(post_oui_delay);
// similarly, mode switch can cause loss of cable ID
dpcd_update_cable_id(link);
dpcd_write_cable_id_to_dprx(link);
skip_video_pattern = true;
@ -3236,9 +3252,16 @@ bool dc_link_setup_psr(struct dc_link *link,
/*skip power down the single pipe since it blocks the cstate*/
#if defined(CONFIG_DRM_AMD_DC_DCN)
if (link->ctx->asic_id.chip_family >= FAMILY_RV) {
psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
if (link->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP && !dc->debug.disable_z10)
psr_context->psr_level.bits.SKIP_CRTC_DISABLE = false;
switch(link->ctx->asic_id.chip_family) {
case FAMILY_YELLOW_CARP:
case AMDGPU_FAMILY_GC_10_3_6:
if(!dc->debug.disable_z10)
psr_context->psr_level.bits.SKIP_CRTC_DISABLE = false;
break;
default:
psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
break;
}
}
#else
if (link->ctx->asic_id.chip_family >= FAMILY_RV)
@ -3905,7 +3928,7 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
&link->mst_stream_alloc_table);
break;
case DP_UNKNOWN_ENCODING:
DC_LOG_ERROR("Failure: unknown encoding format\n");
DC_LOG_DEBUG("Unknown encoding format\n");
return DC_ERROR_UNEXPECTED;
}

3
drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
View File

@ -298,6 +298,9 @@ static uint32_t defer_delay_converter_wa(
if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER &&
link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_0080E1 &&
(link->dpcd_caps.branch_fw_revision[0] < 0x01 ||
(link->dpcd_caps.branch_fw_revision[0] == 0x01 &&
link->dpcd_caps.branch_fw_revision[1] < 0x40)) &&
!memcmp(link->dpcd_caps.branch_dev_name,
DP_VGA_DONGLE_BRANCH_DEV_NAME,
sizeof(link->dpcd_caps.branch_dev_name)))

232
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
View File

@ -51,6 +51,13 @@ static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";
#include "link_dpcd.h"
#ifndef MAX
#define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
#endif
#ifndef MIN
#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
#endif
/* maximum pre emphasis level allowed for each voltage swing level*/
static const enum dc_pre_emphasis
voltage_swing_to_pre_emphasis[] = { PRE_EMPHASIS_LEVEL3,
@ -2294,7 +2301,96 @@ static enum link_training_result dp_perform_128b_132b_link_training(
return result;
}
static enum link_training_result dc_link_dp_perform_fixed_vs_pe_training_sequence(
static enum link_training_result perform_fixed_vs_pe_nontransparent_training_sequence(
struct dc_link *link,
const struct link_resource *link_res,
struct link_training_settings *lt_settings)
{
enum link_training_result status = LINK_TRAINING_SUCCESS;
uint8_t lane = 0;
uint8_t toggle_rate = 0x6;
uint8_t target_rate = 0x6;
bool apply_toggle_rate_wa = false;
uint8_t repeater_cnt;
uint8_t repeater_id;
/* Fixed VS/PE specific: Force CR AUX RD Interval to at least 16ms */
if (lt_settings->cr_pattern_time < 16000)
lt_settings->cr_pattern_time = 16000;
/* Fixed VS/PE specific: Toggle link rate */
apply_toggle_rate_wa = (link->vendor_specific_lttpr_link_rate_wa == target_rate);
target_rate = get_dpcd_link_rate(&lt_settings->link_settings);
toggle_rate = (target_rate == 0x6) ? 0xA : 0x6;
if (apply_toggle_rate_wa)
lt_settings->link_settings.link_rate = toggle_rate;
if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
start_clock_recovery_pattern_early(link, link_res, lt_settings, DPRX);
/* 1. set link rate, lane count and spread. */
dpcd_set_link_settings(link, lt_settings);
/* Fixed VS/PE specific: Toggle link rate back*/
if (apply_toggle_rate_wa) {
core_link_write_dpcd(
link,
DP_LINK_BW_SET,
&target_rate,
1);
}
link->vendor_specific_lttpr_link_rate_wa = target_rate;
if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
/* 2. perform link training (set link training done
* to false is done as well)
*/
repeater_cnt = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
for (repeater_id = repeater_cnt; (repeater_id > 0 && status == LINK_TRAINING_SUCCESS);
repeater_id--) {
status = perform_clock_recovery_sequence(link, link_res, lt_settings, repeater_id);
if (status != LINK_TRAINING_SUCCESS) {
repeater_training_done(link, repeater_id);
break;
}
status = perform_channel_equalization_sequence(link,
link_res,
lt_settings,
repeater_id);
repeater_training_done(link, repeater_id);
if (status != LINK_TRAINING_SUCCESS)
break;
for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
lt_settings->dpcd_lane_settings[lane].raw = 0;
lt_settings->hw_lane_settings[lane].VOLTAGE_SWING = 0;
lt_settings->hw_lane_settings[lane].PRE_EMPHASIS = 0;
}
}
}
if (status == LINK_TRAINING_SUCCESS) {
status = perform_clock_recovery_sequence(link, link_res, lt_settings, DPRX);
if (status == LINK_TRAINING_SUCCESS) {
status = perform_channel_equalization_sequence(link,
link_res,
lt_settings,
DPRX);
}
}
return status;
}
static enum link_training_result dp_perform_fixed_vs_pe_training_sequence(
struct dc_link *link,
const struct link_resource *link_res,
struct link_training_settings *lt_settings)
@ -2318,6 +2414,11 @@ static enum link_training_result dc_link_dp_perform_fixed_vs_pe_training_sequenc
ASSERT(dp_get_link_encoding_format(&lt_settings->link_settings) ==
DP_8b_10b_ENCODING);
if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
status = perform_fixed_vs_pe_nontransparent_training_sequence(link, link_res, lt_settings);
return status;
}
if (offset != 0xFF) {
vendor_lttpr_write_address +=
((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
@ -2664,10 +2765,8 @@ enum link_training_result dc_link_dp_perform_link_training(
* Per DP specs starting from here, DPTX device shall not issue
* Non-LT AUX transactions inside training mode.
*/
if (!link->dc->debug.apply_vendor_specific_lttpr_wa &&
(link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
link->lttpr_mode == LTTPR_MODE_TRANSPARENT)
status = dc_link_dp_perform_fixed_vs_pe_training_sequence(link, link_res, &lt_settings);
if (link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN)
status = dp_perform_fixed_vs_pe_training_sequence(link, link_res, &lt_settings);
else if (encoding == DP_8b_10b_ENCODING)
status = dp_perform_8b_10b_link_training(link, link_res, &lt_settings);
else if (encoding == DP_128b_132b_ENCODING)
@ -2986,11 +3085,11 @@ static enum dc_link_rate get_cable_max_link_rate(struct dc_link *link)
{
enum dc_link_rate cable_max_link_rate = LINK_RATE_HIGH3;
if (link->dpcd_caps.cable_attributes.bits.UHBR10_20_CAPABILITY & DP_UHBR20)
if (link->dpcd_caps.cable_id.bits.UHBR10_20_CAPABILITY & DP_UHBR20)
cable_max_link_rate = LINK_RATE_UHBR20;
else if (link->dpcd_caps.cable_attributes.bits.UHBR13_5_CAPABILITY)
else if (link->dpcd_caps.cable_id.bits.UHBR13_5_CAPABILITY)
cable_max_link_rate = LINK_RATE_UHBR13_5;
else if (link->dpcd_caps.cable_attributes.bits.UHBR10_20_CAPABILITY & DP_UHBR10)
else if (link->dpcd_caps.cable_id.bits.UHBR10_20_CAPABILITY & DP_UHBR10)
cable_max_link_rate = LINK_RATE_UHBR10;
return cable_max_link_rate;
@ -5051,11 +5150,52 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link)
return is_lttpr_present;
}
static bool is_usbc_connector(struct dc_link *link)
static bool get_usbc_cable_id(struct dc_link *link, union dp_cable_id *cable_id)
{
return link->link_enc &&
link->link_enc->features.flags.bits.DP_IS_USB_C;
union dmub_rb_cmd cmd;
if (!link->ctx->dmub_srv ||
link->ep_type != DISPLAY_ENDPOINT_PHY ||
link->link_enc->features.flags.bits.DP_IS_USB_C == 0)
return false;
memset(&cmd, 0, sizeof(cmd));
cmd.cable_id.header.type = DMUB_CMD_GET_USBC_CABLE_ID;
cmd.cable_id.header.payload_bytes = sizeof(cmd.cable_id.data);
cmd.cable_id.data.input.phy_inst = resource_transmitter_to_phy_idx(
link->dc, link->link_enc->transmitter);
if (dc_dmub_srv_cmd_with_reply_data(link->ctx->dmub_srv, &cmd) &&
cmd.cable_id.header.ret_status == 1)
cable_id->raw = cmd.cable_id.data.output_raw;
return cmd.cable_id.header.ret_status == 1;
}
static union dp_cable_id intersect_cable_id(
union dp_cable_id *a, union dp_cable_id *b)
{
union dp_cable_id out;
out.bits.UHBR10_20_CAPABILITY = MIN(a->bits.UHBR10_20_CAPABILITY,
b->bits.UHBR10_20_CAPABILITY);
out.bits.UHBR13_5_CAPABILITY = MIN(a->bits.UHBR13_5_CAPABILITY,
b->bits.UHBR13_5_CAPABILITY);
out.bits.CABLE_TYPE = MAX(a->bits.CABLE_TYPE, b->bits.CABLE_TYPE);
return out;
}
static void retrieve_cable_id(struct dc_link *link)
{
union dp_cable_id usbc_cable_id;
link->dpcd_caps.cable_id.raw = 0;
core_link_read_dpcd(link, DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX,
&link->dpcd_caps.cable_id.raw, sizeof(uint8_t));
if (get_usbc_cable_id(link, &usbc_cable_id))
link->dpcd_caps.cable_id = intersect_cable_id(
&link->dpcd_caps.cable_id, &usbc_cable_id);
}
static bool retrieve_link_cap(struct dc_link *link)
@ -5114,9 +5254,6 @@ static bool retrieve_link_cap(struct dc_link *link)
*/
msleep(post_oui_delay);
/* Read cable ID and update receiver */
dpcd_update_cable_id(link);
for (i = 0; i < read_dpcd_retry_cnt; i++) {
status = core_link_read_dpcd(
link,
@ -5236,7 +5373,8 @@ static bool retrieve_link_cap(struct dc_link *link)
edp_config_cap.bits.ALT_SCRAMBLER_RESET;
link->dpcd_caps.dpcd_display_control_capable =
edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
link->dpcd_caps.channel_coding_cap.raw =
dpcd_data[DP_MAIN_LINK_CHANNEL_CODING - DP_DPCD_REV];
link->test_pattern_enabled = false;
link->compliance_test_state.raw = 0;
@ -5363,8 +5501,6 @@ static bool retrieve_link_cap(struct dc_link *link)
if (!dpcd_read_sink_ext_caps(link))
link->dpcd_sink_ext_caps.raw = 0;
link->dpcd_caps.channel_coding_cap.raw = dpcd_data[DP_MAIN_LINK_CHANNEL_CODING_CAP - DP_DPCD_REV];
if (link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED) {
DC_LOG_DP2("128b/132b encoding is supported at link %d", link->link_index);
@ -5410,6 +5546,9 @@ static bool retrieve_link_cap(struct dc_link *link)
DC_LOG_DP2("\tFEC aggregated error counters are supported");
}
retrieve_cable_id(link);
dpcd_write_cable_id_to_dprx(link);
/* Connectivity log: detection */
CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
@ -5565,6 +5704,34 @@ void detect_edp_sink_caps(struct dc_link *link)
(backlight_adj_cap & DP_EDP_DYNAMIC_BACKLIGHT_CAP) ? true:false;
dc_link_set_default_brightness_aux(link);
core_link_read_dpcd(link, DP_EDP_DPCD_REV,
&link->dpcd_caps.edp_rev,
sizeof(link->dpcd_caps.edp_rev));
/*
* PSR is only valid for eDP v1.3 or higher.
*/
if (link->dpcd_caps.edp_rev >= DP_EDP_13) {
core_link_read_dpcd(link, DP_PSR_SUPPORT,
&link->dpcd_caps.psr_info.psr_version,
sizeof(link->dpcd_caps.psr_info.psr_version));
core_link_read_dpcd(link, DP_PSR_CAPS,
&link->dpcd_caps.psr_info.psr_dpcd_caps.raw,
sizeof(link->dpcd_caps.psr_info.psr_dpcd_caps.raw));
if (link->dpcd_caps.psr_info.psr_dpcd_caps.bits.Y_COORDINATE_REQUIRED) {
core_link_read_dpcd(link, DP_PSR2_SU_Y_GRANULARITY,
&link->dpcd_caps.psr_info.psr2_su_y_granularity_cap,
sizeof(link->dpcd_caps.psr_info.psr2_su_y_granularity_cap));
}
}
/*
* ALPM is only valid for eDP v1.4 or higher.
*/
if (link->dpcd_caps.dpcd_rev.raw >= DP_EDP_14)
core_link_read_dpcd(link, DP_RECEIVER_ALPM_CAP,
&link->dpcd_caps.alpm_caps.raw,
sizeof(link->dpcd_caps.alpm_caps.raw));
}
void dc_link_dp_enable_hpd(const struct dc_link *link)
@ -6314,29 +6481,18 @@ void dpcd_set_source_specific_data(struct dc_link *link)
}
}
void dpcd_update_cable_id(struct dc_link *link)
void dpcd_write_cable_id_to_dprx(struct dc_link *link)
{
struct link_encoder *link_enc = NULL;
link_enc = link_enc_cfg_get_link_enc(link);
if (!link_enc ||
!link_enc->features.flags.bits.IS_UHBR10_CAPABLE ||
link->dprx_status.cable_id_updated)
if (!link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED ||
link->dpcd_caps.cable_id.raw == 0 ||
link->dprx_states.cable_id_written)
return;
/* Retrieve cable attributes */
if (!is_usbc_connector(link))
core_link_read_dpcd(link, DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX,
&link->dpcd_caps.cable_attributes.raw,
sizeof(uint8_t));
/* Update receiver with cable attributes */
core_link_write_dpcd(link, DP_CABLE_ATTRIBUTES_UPDATED_BY_DPTX,
&link->dpcd_caps.cable_attributes.raw,
sizeof(link->dpcd_caps.cable_attributes.raw));
&link->dpcd_caps.cable_id.raw,
sizeof(link->dpcd_caps.cable_id.raw));
link->dprx_status.cable_id_updated = 1;
link->dprx_states.cable_id_written = 1;
}
bool dc_link_set_backlight_level_nits(struct dc_link *link,
@ -6737,9 +6893,9 @@ void edp_panel_backlight_power_on(struct dc_link *link)
link->dc->hwss.edp_backlight_control(link, true);
}
void dc_link_dp_clear_rx_status(struct dc_link *link)
void dc_link_clear_dprx_states(struct dc_link *link)
{
memset(&link->dprx_status, 0, sizeof(link->dprx_status));
memset(&link->dprx_states, 0, sizeof(link->dprx_states));
}
void dp_receiver_power_ctrl(struct dc_link *link, bool on)

10
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
View File

@ -66,6 +66,7 @@
#include "dcn302/dcn302_resource.h"
#include "dcn303/dcn303_resource.h"
#include "dcn31/dcn31_resource.h"
#include "dcn315/dcn315_resource.h"
#include "dcn316/dcn316_resource.h"
#endif
@ -156,6 +157,10 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
if (ASICREV_IS_YELLOW_CARP(asic_id.hw_internal_rev))
dc_version = DCN_VERSION_3_1;
break;
case AMDGPU_FAMILY_GC_10_3_6:
if (ASICREV_IS_GC_10_3_6(asic_id.hw_internal_rev))
dc_version = DCN_VERSION_3_15;
break;
case AMDGPU_FAMILY_GC_10_3_7:
if (ASICREV_IS_GC_10_3_7(asic_id.hw_internal_rev))
dc_version = DCN_VERSION_3_16;
@ -251,6 +256,9 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc,
case DCN_VERSION_3_1:
res_pool = dcn31_create_resource_pool(init_data, dc);
break;
case DCN_VERSION_3_15:
res_pool = dcn315_create_resource_pool(init_data, dc);
break;
case DCN_VERSION_3_16:
res_pool = dcn316_create_resource_pool(init_data, dc);
break;
@ -1916,7 +1924,7 @@ static struct audio *find_first_free_audio(
return pool->audios[i];
}
}
return 0;
return NULL;
}
/*

7
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
View File

@ -273,6 +273,8 @@ static void program_cursor_attributes(
if (!pipe_to_program) {
pipe_to_program = pipe_ctx;
dc->hwss.cursor_lock(dc, pipe_to_program, true);
if (pipe_to_program->next_odm_pipe)
dc->hwss.cursor_lock(dc, pipe_to_program->next_odm_pipe, true);
}
dc->hwss.set_cursor_attribute(pipe_ctx);
@ -280,8 +282,11 @@ static void program_cursor_attributes(
dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
}
if (pipe_to_program)
if (pipe_to_program) {
dc->hwss.cursor_lock(dc, pipe_to_program, false);
if (pipe_to_program->next_odm_pipe)
dc->hwss.cursor_lock(dc, pipe_to_program->next_odm_pipe, false);
}
}
#ifndef TRIM_FSFT

9
drivers/gpu/drm/amd/display/dc/dc.h
View File

@ -47,7 +47,7 @@ struct aux_payload;
struct set_config_cmd_payload;
struct dmub_notification;
#define DC_VER "3.2.173"
#define DC_VER "3.2.174"
#define MAX_SURFACES 3
#define MAX_PLANES 6
@ -709,6 +709,7 @@ struct dc_debug_options {
union dpia_debug_options dpia_debug;
#endif
bool apply_vendor_specific_lttpr_wa;
bool ignore_dpref_ss;
};
struct gpu_info_soc_bounding_box_v1_0;
@ -1230,14 +1231,16 @@ struct dpcd_caps {
union dpcd_fec_capability fec_cap;
struct dpcd_dsc_capabilities dsc_caps;
struct dc_lttpr_caps lttpr_caps;
struct psr_caps psr_caps;
struct dpcd_usb4_dp_tunneling_info usb4_dp_tun_info;
union dp_128b_132b_supported_link_rates dp_128b_132b_supported_link_rates;
union dp_main_line_channel_coding_cap channel_coding_cap;
union dp_sink_video_fallback_formats fallback_formats;
union dp_fec_capability1 fec_cap1;
union dp_cable_attributes cable_attributes;
union dp_cable_id cable_id;
uint8_t edp_rev;
union edp_alpm_caps alpm_caps;
struct edp_psr_info psr_info;
};
union dpcd_sink_ext_caps {

31
drivers/gpu/drm/amd/display/dc/dc_dp_types.h
View File

@ -1018,7 +1018,7 @@ union dp_fec_capability1 {
uint8_t raw;
};
union dp_cable_attributes {
union dp_cable_id {
struct {
uint8_t UHBR10_20_CAPABILITY :2;
uint8_t UHBR13_5_CAPABILITY :1;
@ -1068,4 +1068,33 @@ union dp_128b_132b_training_aux_rd_interval {
uint8_t raw;
};
union edp_alpm_caps {
struct {
uint8_t AUX_WAKE_ALPM_CAP :1;
uint8_t PM_STATE_2A_SUPPORT :1;
uint8_t AUX_LESS_ALPM_CAP :1;
uint8_t RESERVED :5;
} bits;
uint8_t raw;
};
union edp_psr_dpcd_caps {
struct {
uint8_t LINK_TRAINING_ON_EXIT_NOT_REQUIRED :1;
uint8_t PSR_SETUP_TIME :3;
uint8_t Y_COORDINATE_REQUIRED :1;
uint8_t SU_GRANULARITY_REQUIRED :1;
uint8_t FRAME_SYNC_IS_NOT_NEEDED_FOR_SU :1;
uint8_t RESERVED :1;
} bits;
uint8_t raw;
};
struct edp_psr_info {
uint8_t psr_version;
union edp_psr_dpcd_caps psr_dpcd_caps;
uint8_t psr2_su_y_granularity_cap;
uint8_t force_psrsu_cap;
};
#endif /* DC_DP_TYPES_H */

8
drivers/gpu/drm/amd/display/dc/dc_link.h
View File

@ -43,8 +43,8 @@ struct dc_link_status {
struct dpcd_caps *dpcd_caps;
};
struct dp_receiver_status {
bool cable_id_updated;
struct dprx_states {
bool cable_id_written;
};
/* DP MST stream allocation (payload bandwidth number) */
@ -205,7 +205,7 @@ struct dc_link {
struct link_mst_stream_allocation_table mst_stream_alloc_table;
struct dc_link_status link_status;
struct dp_receiver_status dprx_status;
struct dprx_states dprx_states;
struct link_trace link_trace;
struct gpio *hpd_gpio;
@ -466,7 +466,7 @@ void dc_link_get_cur_link_res(const struct dc_link *link,
void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map);
/* restore link resource allocation state from a snapshot */
void dc_restore_link_res_map(const struct dc *dc, uint32_t *map);
void dc_link_dp_clear_rx_status(struct dc_link *link);
void dc_link_clear_dprx_states(struct dc_link *link);
struct gpio *get_hpd_gpio(struct dc_bios *dcb,
struct graphics_object_id link_id,
struct gpio_service *gpio_service);

4
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
View File

@ -1585,7 +1585,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(
hws->funcs.enable_stream_timing(pipe_ctx, context, dc);
}
pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL;
pipe_ctx->stream->link->psr_settings.psr_feature_enabled = false;
@ -2722,7 +2722,7 @@ static void dce110_program_front_end_for_pipe(
pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL;
program_scaler(dc, pipe_ctx);

2
drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
View File

@ -862,7 +862,7 @@ static struct clock_source *find_matching_pll(
return NULL;
}
return 0;
return NULL;
}
static enum dc_status build_mapped_resource(

3
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
View File

@ -2060,14 +2060,11 @@ static int dcn10_align_pixel_clocks(struct dc *dc, int group_size,
uint32_t embedded_pix_clk_100hz;
uint16_t embedded_h_total;
uint16_t embedded_v_total;
bool clamshell_closed = false;
uint32_t dp_ref_clk_100hz =
dc->res_pool->dp_clock_source->ctx->dc->clk_mgr->dprefclk_khz*10;
if (dc->config.vblank_alignment_dto_params &&
dc->res_pool->dp_clock_source->funcs->override_dp_pix_clk) {
clamshell_closed =
(dc->config.vblank_alignment_dto_params >> 63);
embedded_h_total =
(dc->config.vblank_alignment_dto_params >> 32) & 0x7FFF;
embedded_v_total =

12
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
View File

@ -1818,6 +1818,7 @@ void dcn20_prepare_bandwidth(
struct dc_state *context)
{
struct hubbub *hubbub = dc->res_pool->hubbub;
unsigned int compbuf_size_kb = 0;
dc->clk_mgr->funcs->update_clocks(
dc->clk_mgr,
@ -1829,9 +1830,16 @@ void dcn20_prepare_bandwidth(
&context->bw_ctx.bw.dcn.watermarks,
dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
false);
/* decrease compbuf size */
if (hubbub->funcs->program_compbuf_size)
hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, false);
if (hubbub->funcs->program_compbuf_size) {
if (context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes)
compbuf_size_kb = context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes;
else
compbuf_size_kb = context->bw_ctx.bw.dcn.compbuf_size_kb;
hubbub->funcs->program_compbuf_size(hubbub, compbuf_size_kb, false);
}
}
void dcn20_optimize_bandwidth(

1
drivers/gpu/drm/amd/display/dc/dcn201/dcn201_init.c
View File

@ -27,6 +27,7 @@
#include "dcn10/dcn10_hw_sequencer.h"
#include "dcn20/dcn20_hwseq.h"
#include "dcn201_hwseq.h"
#include "dcn201_init.h"
static const struct hw_sequencer_funcs dcn201_funcs = {
.program_gamut_remap = dcn10_program_gamut_remap,

56
drivers/gpu/drm/amd/display/dc/dcn315/Makefile Normal file
View File

@ -0,0 +1,56 @@
#
# Copyright © 2021 Advanced Micro Devices, Inc.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
# to deal in the Software without restriction, including without limitation
# the rights to use, copy, modify, merge, publish, distribute, sublicense,
# and/or sell copies of the Software, and to permit persons to whom the
# Software is furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
# OTHER DEALINGS IN THE SOFTWARE.
#
# Authors: AMD
#
# Makefile for dcn315.
DCN315 = dcn315_resource.o
ifdef CONFIG_X86
CFLAGS_$(AMDDALPATH)/dc/dcn315/dcn315_resource.o := -msse
endif
ifdef CONFIG_PPC64
CFLAGS_$(AMDDALPATH)/dc/dcn315/dcn315_resource.o := -mhard-float -maltivec
endif
ifdef CONFIG_CC_IS_GCC
ifeq ($(call cc-ifversion, -lt, 0701, y), y)
IS_OLD_GCC = 1
endif
CFLAGS_$(AMDDALPATH)/dc/dcn315/dcn315_resource.o += -mhard-float
endif
ifdef CONFIG_X86
ifdef IS_OLD_GCC
# Stack alignment mismatch, proceed with caution.
# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
# (8B stack alignment).
CFLAGS_$(AMDDALPATH)/dc/dcn315/dcn315_resource.o += -mpreferred-stack-boundary=4
else
CFLAGS_$(AMDDALPATH)/dc/dcn315/dcn315_resource.o += -msse2
endif
endif
AMD_DAL_DCN315 = $(addprefix $(AMDDALPATH)/dc/dcn315/,$(DCN315))
AMD_DISPLAY_FILES += $(AMD_DAL_DCN315)

2304
drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c Normal file
View File

File diff suppressed because it is too large Load Diff

42
drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.h Normal file
View File

@ -0,0 +1,42 @@
/*
* Copyright 2021 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef _DCN315_RESOURCE_H_
#define _DCN315_RESOURCE_H_
#include "core_types.h"
#define TO_DCN315_RES_POOL(pool)\
container_of(pool, struct dcn315_resource_pool, base)
struct dcn315_resource_pool {
struct resource_pool base;
};
struct resource_pool *dcn315_create_resource_pool(
const struct dc_init_data *init_data,
struct dc *dc);
#endif /* _DCN315_RESOURCE_H_ */

1
drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
View File

@ -141,6 +141,7 @@ struct _vcs_dpi_ip_params_st {
unsigned int odm_capable;
unsigned int rob_buffer_size_kbytes;
unsigned int det_buffer_size_kbytes;
unsigned int min_comp_buffer_size_kbytes;
unsigned int dpte_buffer_size_in_pte_reqs_luma;
unsigned int dpte_buffer_size_in_pte_reqs_chroma;
unsigned int pde_proc_buffer_size_64k_reqs;

8
drivers/gpu/drm/amd/display/dc/gpio/Makefile
View File

@ -106,6 +106,14 @@ GPIO_DCN30 = hw_translate_dcn30.o hw_factory_dcn30.o
AMD_DAL_GPIO_DCN30 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn30/,$(GPIO_DCN30))
AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN30)
###############################################################################
# DCN 3.15
###############################################################################
GPIO_DCN315 = hw_translate_dcn315.o hw_factory_dcn315.o
AMD_DAL_GPIO_DCN315 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn315/,$(GPIO_DCN315))
AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN315)
endif
###############################################################################
# Diagnostics on FPGA

260
drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c Normal file
View File

@ -0,0 +1,260 @@
/*
* Copyright 2021 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
#include "include/gpio_types.h"
#include "../hw_factory.h"
#include "../hw_gpio.h"
#include "../hw_ddc.h"
#include "../hw_hpd.h"
#include "../hw_generic.h"
#include "hw_factory_dcn315.h"
#include "dcn/dcn_3_1_5_offset.h"
#include "dcn/dcn_3_1_5_sh_mask.h"
#include "reg_helper.h"
#include "../hpd_regs.h"
/* begin *********************
* macros to expend register list macro defined in HW object header file */
#define DCN_BASE__INST0_SEG0 0x00000012
#define DCN_BASE__INST0_SEG1 0x000000C0
#define DCN_BASE__INST0_SEG2 0x000034C0
#define DCN_BASE__INST0_SEG3 0x00009000
#define DCN_BASE__INST0_SEG4 0x02403C00
#define DCN_BASE__INST0_SEG5 0
/* DCN */
#define block HPD
#define reg_num 0
#undef BASE_INNER
#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
#define BASE(seg) BASE_INNER(seg)
#define REG(reg_name)\
BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
#define SF_HPD(reg_name, field_name, post_fix)\
.field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
#define REGI(reg_name, block, id)\
BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
reg ## block ## id ## _ ## reg_name
#define SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
/* macros to expend register list macro defined in HW object header file
* end *********************/
#define hpd_regs(id) \
{\
HPD_REG_LIST(id)\
}
static const struct hpd_registers hpd_regs[] = {
hpd_regs(0),
hpd_regs(1),
hpd_regs(2),
hpd_regs(3),
hpd_regs(4),
};
static const struct hpd_sh_mask hpd_shift = {
HPD_MASK_SH_LIST(__SHIFT)
};
static const struct hpd_sh_mask hpd_mask = {
HPD_MASK_SH_LIST(_MASK)
};
#include "../ddc_regs.h"
/* set field name */
#define SF_DDC(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
static const struct ddc_registers ddc_data_regs_dcn[] = {
ddc_data_regs_dcn2(1),
ddc_data_regs_dcn2(2),
ddc_data_regs_dcn2(3),
ddc_data_regs_dcn2(4),
ddc_data_regs_dcn2(5),
{
DDC_GPIO_VGA_REG_LIST(DATA),
.ddc_setup = 0,
.phy_aux_cntl = 0,
.dc_gpio_aux_ctrl_5 = 0
}
};
static const struct ddc_registers ddc_clk_regs_dcn[] = {
ddc_clk_regs_dcn2(1),
ddc_clk_regs_dcn2(2),
ddc_clk_regs_dcn2(3),
ddc_clk_regs_dcn2(4),
ddc_clk_regs_dcn2(5),
{
DDC_GPIO_VGA_REG_LIST(CLK),
.ddc_setup = 0,
.phy_aux_cntl = 0,
.dc_gpio_aux_ctrl_5 = 0
}
};
static const struct ddc_sh_mask ddc_shift[] = {
DDC_MASK_SH_LIST_DCN2(__SHIFT, 1),
DDC_MASK_SH_LIST_DCN2(__SHIFT, 2),
DDC_MASK_SH_LIST_DCN2(__SHIFT, 3),
DDC_MASK_SH_LIST_DCN2(__SHIFT, 4),
DDC_MASK_SH_LIST_DCN2(__SHIFT, 5),
DDC_MASK_SH_LIST_DCN2(__SHIFT, 6)
};
static const struct ddc_sh_mask ddc_mask[] = {
DDC_MASK_SH_LIST_DCN2(_MASK, 1),
DDC_MASK_SH_LIST_DCN2(_MASK, 2),
DDC_MASK_SH_LIST_DCN2(_MASK, 3),
DDC_MASK_SH_LIST_DCN2(_MASK, 4),
DDC_MASK_SH_LIST_DCN2(_MASK, 5),
DDC_MASK_SH_LIST_DCN2(_MASK, 6)
};
#include "../generic_regs.h"
/* set field name */
#define SF_GENERIC(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
#define generic_regs(id) \
{\
GENERIC_REG_LIST(id)\
}
static const struct generic_registers generic_regs[] = {
generic_regs(A),
generic_regs(B),
};
static const struct generic_sh_mask generic_shift[] = {
GENERIC_MASK_SH_LIST(__SHIFT, A),
GENERIC_MASK_SH_LIST(__SHIFT, B),
};
static const struct generic_sh_mask generic_mask[] = {
GENERIC_MASK_SH_LIST(_MASK, A),
GENERIC_MASK_SH_LIST(_MASK, B),
};
static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en)
{
struct hw_generic *generic = HW_GENERIC_FROM_BASE(pin);
generic->regs = &generic_regs[en];
generic->shifts = &generic_shift[en];
generic->masks = &generic_mask[en];
generic->base.regs = &generic_regs[en].gpio;
}
static void define_ddc_registers(
struct hw_gpio_pin *pin,
uint32_t en)
{
struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);
switch (pin->id) {
case GPIO_ID_DDC_DATA:
ddc->regs = &ddc_data_regs_dcn[en];
ddc->base.regs = &ddc_data_regs_dcn[en].gpio;
break;
case GPIO_ID_DDC_CLOCK:
ddc->regs = &ddc_clk_regs_dcn[en];
ddc->base.regs = &ddc_clk_regs_dcn[en].gpio;
break;
default:
ASSERT_CRITICAL(false);
return;
}
ddc->shifts = &ddc_shift[en];
ddc->masks = &ddc_mask[en];
}
static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)
{
struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin);
hpd->regs = &hpd_regs[en];
hpd->shifts = &hpd_shift;
hpd->masks = &hpd_mask;
hpd->base.regs = &hpd_regs[en].gpio;
}
/* fucntion table */
static const struct hw_factory_funcs funcs = {
.init_ddc_data = dal_hw_ddc_init,
.init_generic = dal_hw_generic_init,
.init_hpd = dal_hw_hpd_init,
.get_ddc_pin = dal_hw_ddc_get_pin,
.get_hpd_pin = dal_hw_hpd_get_pin,
.get_generic_pin = dal_hw_generic_get_pin,
.define_hpd_registers = define_hpd_registers,
.define_ddc_registers = define_ddc_registers,
.define_generic_registers = define_generic_registers
};
/*
* dal_hw_factory_dcn10_init
*
* @brief
* Initialize HW factory function pointers and pin info
*
* @param
* struct hw_factory *factory - [out] struct of function pointers
*/
void dal_hw_factory_dcn315_init(struct hw_factory *factory)
{
/*TODO check ASIC CAPs*/
factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
factory->number_of_pins[GPIO_ID_GENERIC] = 4;
factory->number_of_pins[GPIO_ID_HPD] = 6;
factory->number_of_pins[GPIO_ID_GPIO_PAD] = 28;
factory->number_of_pins[GPIO_ID_VIP_PAD] = 0;
factory->number_of_pins[GPIO_ID_SYNC] = 0;
factory->number_of_pins[GPIO_ID_GSL] = 0;/*add this*/
factory->funcs = &funcs;
}

31
drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.h Normal file
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@ -0,0 +1,31 @@
/*
* Copyright 2021 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_HW_FACTORY_DCN315_H__
#define __DAL_HW_FACTORY_DCN315_H__
/* Initialize HW factory function pointers and pin info */
void dal_hw_factory_dcn315_init(struct hw_factory *factory);
#endif /* __DAL_HW_FACTORY_DCN315_H__ */

374
drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c Normal file
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@ -0,0 +1,374 @@
/*
* Copyright 2021 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "hw_translate_dcn315.h"
#include "dm_services.h"
#include "include/gpio_types.h"
#include "../hw_translate.h"
#include "dcn/dcn_3_1_5_offset.h"
#include "dcn/dcn_3_1_5_sh_mask.h"
/* begin *********************
* macros to expend register list macro defined in HW object header file */
#define DCN_BASE__INST0_SEG0 0x00000012
#define DCN_BASE__INST0_SEG1 0x000000C0
#define DCN_BASE__INST0_SEG2 0x000034C0
#define DCN_BASE__INST0_SEG3 0x00009000
#define DCN_BASE__INST0_SEG4 0x02403C00
#define DCN_BASE__INST0_SEG5 0
/* DCN */
#define block HPD
#define reg_num 0
#undef BASE_INNER
#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
#define BASE(seg) BASE_INNER(seg)
#undef REG
#define REG(reg_name)\
BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
#define SF_HPD(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
/* macros to expend register list macro defined in HW object header file
* end *********************/
static bool offset_to_id(
uint32_t offset,
uint32_t mask,
enum gpio_id *id,
uint32_t *en)
{
switch (offset) {
/* GENERIC */
case REG(DC_GPIO_GENERIC_A):
*id = GPIO_ID_GENERIC;
switch (mask) {
case DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK:
*en = GPIO_GENERIC_A;
return true;
case DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK:
*en = GPIO_GENERIC_B;
return true;
case DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK:
*en = GPIO_GENERIC_C;
return true;
case DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK:
*en = GPIO_GENERIC_D;
return true;
case DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK:
*en = GPIO_GENERIC_E;
return true;
case DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK:
*en = GPIO_GENERIC_F;
return true;
case DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK:
*en = GPIO_GENERIC_G;
return true;
default:
ASSERT_CRITICAL(false);
return false;
}
break;
/* HPD */
case REG(DC_GPIO_HPD_A):
*id = GPIO_ID_HPD;
switch (mask) {
case DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK:
*en = GPIO_HPD_1;
return true;
case DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK:
*en = GPIO_HPD_2;
return true;
case DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK:
*en = GPIO_HPD_3;
return true;
case DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK:
*en = GPIO_HPD_4;
return true;
case DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK:
*en = GPIO_HPD_5;
return true;
case DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK:
*en = GPIO_HPD_6;
return true;
default:
ASSERT_CRITICAL(false);
return false;
}
break;
/* REG(DC_GPIO_GENLK_MASK */
case REG(DC_GPIO_GENLK_A):
*id = GPIO_ID_GSL;
switch (mask) {
case DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK:
*en = GPIO_GSL_GENLOCK_CLOCK;
return true;
case DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK:
*en = GPIO_GSL_GENLOCK_VSYNC;
return true;
case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK:
*en = GPIO_GSL_SWAPLOCK_A;
return true;
case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK:
*en = GPIO_GSL_SWAPLOCK_B;
return true;
default:
ASSERT_CRITICAL(false);
return false;
}
break;
/* DDC */
/* we don't care about the GPIO_ID for DDC
* in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK
* directly in the create method
*/
case REG(DC_GPIO_DDC1_A):
*en = GPIO_DDC_LINE_DDC1;
return true;
case REG(DC_GPIO_DDC2_A):
*en = GPIO_DDC_LINE_DDC2;
return true;
case REG(DC_GPIO_DDC3_A):
*en = GPIO_DDC_LINE_DDC3;
return true;
case REG(DC_GPIO_DDC4_A):
*en = GPIO_DDC_LINE_DDC4;
return true;
case REG(DC_GPIO_DDC5_A):
*en = GPIO_DDC_LINE_DDC5;
return true;
case REG(DC_GPIO_DDCVGA_A):
*en = GPIO_DDC_LINE_DDC_VGA;
return true;
/*
* case REG(DC_GPIO_I2CPAD_A): not exit
* case REG(DC_GPIO_PWRSEQ_A):
* case REG(DC_GPIO_PAD_STRENGTH_1):
* case REG(DC_GPIO_PAD_STRENGTH_2):
* case REG(DC_GPIO_DEBUG):
*/
/* UNEXPECTED */
default:
/* case REG(DC_GPIO_SYNCA_A): not exist */
ASSERT_CRITICAL(false);
return false;
}
}
static bool id_to_offset(
enum gpio_id id,
uint32_t en,
struct gpio_pin_info *info)
{
bool result = true;
switch (id) {
case GPIO_ID_DDC_DATA:
info->mask = DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK;
switch (en) {
case GPIO_DDC_LINE_DDC1:
info->offset = REG(DC_GPIO_DDC1_A);
break;
case GPIO_DDC_LINE_DDC2:
info->offset = REG(DC_GPIO_DDC2_A);
break;
case GPIO_DDC_LINE_DDC3:
info->offset = REG(DC_GPIO_DDC3_A);
break;
case GPIO_DDC_LINE_DDC4:
info->offset = REG(DC_GPIO_DDC4_A);
break;
case GPIO_DDC_LINE_DDC5:
info->offset = REG(DC_GPIO_DDC5_A);
break;
case GPIO_DDC_LINE_DDC_VGA:
info->offset = REG(DC_GPIO_DDCVGA_A);
break;
case GPIO_DDC_LINE_I2C_PAD:
default:
ASSERT_CRITICAL(false);
result = false;
}
break;
case GPIO_ID_DDC_CLOCK:
info->mask = DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK;
switch (en) {
case GPIO_DDC_LINE_DDC1:
info->offset = REG(DC_GPIO_DDC1_A);
break;
case GPIO_DDC_LINE_DDC2:
info->offset = REG(DC_GPIO_DDC2_A);
break;
case GPIO_DDC_LINE_DDC3:
info->offset = REG(DC_GPIO_DDC3_A);
break;
case GPIO_DDC_LINE_DDC4:
info->offset = REG(DC_GPIO_DDC4_A);
break;
case GPIO_DDC_LINE_DDC5:
info->offset = REG(DC_GPIO_DDC5_A);
break;
case GPIO_DDC_LINE_DDC_VGA:
info->offset = REG(DC_GPIO_DDCVGA_A);
break;
case GPIO_DDC_LINE_I2C_PAD:
default:
ASSERT_CRITICAL(false);
result = false;
}
break;
case GPIO_ID_GENERIC:
info->offset = REG(DC_GPIO_GENERIC_A);
switch (en) {
case GPIO_GENERIC_A:
info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK;
break;
case GPIO_GENERIC_B:
info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK;
break;
case GPIO_GENERIC_C:
info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK;
break;
case GPIO_GENERIC_D:
info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK;
break;
case GPIO_GENERIC_E:
info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK;
break;
case GPIO_GENERIC_F:
info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK;
break;
case GPIO_GENERIC_G:
info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK;
break;
default:
ASSERT_CRITICAL(false);
result = false;
}
break;
case GPIO_ID_HPD:
info->offset = REG(DC_GPIO_HPD_A);
switch (en) {
case GPIO_HPD_1:
info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;
break;
case GPIO_HPD_2:
info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK;
break;
case GPIO_HPD_3:
info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK;
break;
case GPIO_HPD_4:
info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK;
break;
case GPIO_HPD_5:
info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK;
break;
case GPIO_HPD_6:
info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK;
break;
default:
ASSERT_CRITICAL(false);
result = false;
}
break;
case GPIO_ID_GSL:
switch (en) {
case GPIO_GSL_GENLOCK_CLOCK:
/*not implmented*/
ASSERT_CRITICAL(false);
result = false;
break;
case GPIO_GSL_GENLOCK_VSYNC:
/*not implmented*/
ASSERT_CRITICAL(false);
result = false;
break;
case GPIO_GSL_SWAPLOCK_A:
/*not implmented*/
ASSERT_CRITICAL(false);
result = false;
break;
case GPIO_GSL_SWAPLOCK_B:
/*not implmented*/
ASSERT_CRITICAL(false);
result = false;
break;
default:
ASSERT_CRITICAL(false);
result = false;
}
break;
case GPIO_ID_SYNC:
case GPIO_ID_VIP_PAD:
default:
ASSERT_CRITICAL(false);
result = false;
}
if (result) {
info->offset_y = info->offset + 2;
info->offset_en = info->offset + 1;
info->offset_mask = info->offset - 1;
info->mask_y = info->mask;
info->mask_en = info->mask;
info->mask_mask = info->mask;
}
return result;
}
/* function table */
static const struct hw_translate_funcs funcs = {
.offset_to_id = offset_to_id,
.id_to_offset = id_to_offset,
};
/*
* dal_hw_translate_dcn30_init
*
* @brief
* Initialize Hw translate function pointers.
*
* @param
* struct hw_translate *tr - [out] struct of function pointers
*
*/
void dal_hw_translate_dcn315_init(struct hw_translate *tr)
{
tr->funcs = &funcs;
}

33
drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.h Normal file
View File

@ -0,0 +1,33 @@
/*
* Copyright 2021 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_HW_TRANSLATE_DCN315_H__
#define __DAL_HW_TRANSLATE_DCN315_H__
struct hw_translate;
/* Initialize Hw translate function pointers */
void dal_hw_translate_dcn315_init(struct hw_translate *tr);
#endif /* __DAL_HW_TRANSLATE_DCN315_H__ */

4
drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
View File

@ -53,6 +53,7 @@
#include "dcn20/hw_factory_dcn20.h"
#include "dcn21/hw_factory_dcn21.h"
#include "dcn30/hw_factory_dcn30.h"
#include "dcn315/hw_factory_dcn315.h"
#endif
#include "diagnostics/hw_factory_diag.h"
@ -117,6 +118,9 @@ bool dal_hw_factory_init(
case DCN_VERSION_3_16:
dal_hw_factory_dcn30_init(factory);
return true;
case DCN_VERSION_3_15:
dal_hw_factory_dcn315_init(factory);
return true;
#endif
default:
ASSERT_CRITICAL(false);

4
drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
View File

@ -51,6 +51,7 @@
#include "dcn20/hw_translate_dcn20.h"
#include "dcn21/hw_translate_dcn21.h"
#include "dcn30/hw_translate_dcn30.h"
#include "dcn315/hw_translate_dcn315.h"
#endif
#include "diagnostics/hw_translate_diag.h"
@ -112,6 +113,9 @@ bool dal_hw_translate_init(
case DCN_VERSION_3_16:
dal_hw_translate_dcn30_init(translate);
return true;
case DCN_VERSION_3_15:
dal_hw_translate_dcn315_init(translate);
return true;
#endif
default:

2
drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
View File

@ -106,7 +106,7 @@ bool dp_overwrite_extended_receiver_cap(struct dc_link *link);
void dpcd_set_source_specific_data(struct dc_link *link);
void dpcd_update_cable_id(struct dc_link *link);
void dpcd_write_cable_id_to_dprx(struct dc_link *link);
/* Write DPCD link configuration data. */
enum dc_status dpcd_set_link_settings(

8
drivers/gpu/drm/amd/display/dc/irq/Makefile
View File

@ -137,3 +137,11 @@ AMD_DAL_IRQ_DCN31= $(addprefix $(AMDDALPATH)/dc/irq/dcn31/,$(IRQ_DCN31))
AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN31)
endif
###############################################################################
# DCN 315
###############################################################################
IRQ_DCN315 = irq_service_dcn315.o
AMD_DAL_IRQ_DCN315= $(addprefix $(AMDDALPATH)/dc/irq/dcn315/,$(IRQ_DCN315))
AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN315)

2
drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
View File

@ -40,7 +40,7 @@
#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
enum dc_irq_source to_dal_irq_source_dcn20(
static enum dc_irq_source to_dal_irq_source_dcn20(
struct irq_service *irq_service,
uint32_t src_id,
uint32_t ext_id)

5
drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c
View File

@ -138,11 +138,6 @@ static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
.ack = NULL
};
static const struct irq_source_info_funcs dmub_outbox_irq_info_funcs = {
.set = NULL,
.ack = NULL
};
#undef BASE_INNER
#define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg

14
drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
View File

@ -265,14 +265,6 @@ static const struct irq_source_info_funcs vline0_irq_info_funcs = {
.funcs = &pflip_irq_info_funcs\
}
#define vupdate_int_entry(reg_num)\
[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
IRQ_REG_ENTRY(OTG, reg_num,\
OTG_GLOBAL_SYNC_STATUS, VUPDATE_INT_EN,\
OTG_GLOBAL_SYNC_STATUS, VUPDATE_EVENT_CLEAR),\
.funcs = &vblank_irq_info_funcs\
}
/* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
* of DCE's DC_IRQ_SOURCE_VUPDATEx.
*/
@ -401,12 +393,6 @@ irq_source_info_dcn21[DAL_IRQ_SOURCES_NUMBER] = {
dc_underflow_int_entry(6),
[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
vupdate_int_entry(0),
vupdate_int_entry(1),
vupdate_int_entry(2),
vupdate_int_entry(3),
vupdate_int_entry(4),
vupdate_int_entry(5),
vupdate_no_lock_int_entry(0),
vupdate_no_lock_int_entry(1),
vupdate_no_lock_int_entry(2),

2
drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c
View File

@ -47,7 +47,7 @@
#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
enum dc_irq_source to_dal_irq_source_dcn30(
static enum dc_irq_source to_dal_irq_source_dcn30(
struct irq_service *irq_service,
uint32_t src_id,
uint32_t ext_id)

438
drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c Normal file
View File

@ -0,0 +1,438 @@
/*
* Copyright 2021 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "dm_services.h"
#include "include/logger_interface.h"
#include "../dce110/irq_service_dce110.h"
#include "dcn/dcn_3_1_5_offset.h"
#include "dcn/dcn_3_1_5_sh_mask.h"
#include "irq_service_dcn315.h"
#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
#define DCN_BASE__INST0_SEG0 0x00000012
#define DCN_BASE__INST0_SEG1 0x000000C0
#define DCN_BASE__INST0_SEG2 0x000034C0
#define DCN_BASE__INST0_SEG3 0x00009000
#define DCN_BASE__INST0_SEG4 0x02403C00
#define DCN_BASE__INST0_SEG5 0
static enum dc_irq_source to_dal_irq_source_dcn315(
struct irq_service *irq_service,
uint32_t src_id,
uint32_t ext_id)
{
switch (src_id) {
case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
return DC_IRQ_SOURCE_VBLANK1;
case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
return DC_IRQ_SOURCE_VBLANK2;
case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
return DC_IRQ_SOURCE_VBLANK3;
case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
return DC_IRQ_SOURCE_VBLANK4;
case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
return DC_IRQ_SOURCE_VBLANK5;
case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
return DC_IRQ_SOURCE_VBLANK6;
case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
return DC_IRQ_SOURCE_DC1_VLINE0;
case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
return DC_IRQ_SOURCE_DC2_VLINE0;
case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
return DC_IRQ_SOURCE_DC3_VLINE0;
case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
return DC_IRQ_SOURCE_DC4_VLINE0;
case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
return DC_IRQ_SOURCE_DC5_VLINE0;
case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
return DC_IRQ_SOURCE_DC6_VLINE0;
case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
return DC_IRQ_SOURCE_PFLIP1;
case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
return DC_IRQ_SOURCE_PFLIP2;
case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
return DC_IRQ_SOURCE_PFLIP3;
case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
return DC_IRQ_SOURCE_PFLIP4;
case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
return DC_IRQ_SOURCE_PFLIP5;
case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
return DC_IRQ_SOURCE_PFLIP6;
case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
return DC_IRQ_SOURCE_VUPDATE1;
case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
return DC_IRQ_SOURCE_VUPDATE2;
case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
return DC_IRQ_SOURCE_VUPDATE3;
case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
return DC_IRQ_SOURCE_VUPDATE4;
case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
return DC_IRQ_SOURCE_VUPDATE5;
case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
return DC_IRQ_SOURCE_VUPDATE6;
case DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT:
return DC_IRQ_SOURCE_DMCUB_OUTBOX;
case DCN_1_0__SRCID__DC_HPD1_INT:
/* generic src_id for all HPD and HPDRX interrupts */
switch (ext_id) {
case DCN_1_0__CTXID__DC_HPD1_INT:
return DC_IRQ_SOURCE_HPD1;
case DCN_1_0__CTXID__DC_HPD2_INT:
return DC_IRQ_SOURCE_HPD2;
case DCN_1_0__CTXID__DC_HPD3_INT:
return DC_IRQ_SOURCE_HPD3;
case DCN_1_0__CTXID__DC_HPD4_INT:
return DC_IRQ_SOURCE_HPD4;
case DCN_1_0__CTXID__DC_HPD5_INT:
return DC_IRQ_SOURCE_HPD5;
case DCN_1_0__CTXID__DC_HPD6_INT:
return DC_IRQ_SOURCE_HPD6;
case DCN_1_0__CTXID__DC_HPD1_RX_INT:
return DC_IRQ_SOURCE_HPD1RX;
case DCN_1_0__CTXID__DC_HPD2_RX_INT:
return DC_IRQ_SOURCE_HPD2RX;
case DCN_1_0__CTXID__DC_HPD3_RX_INT:
return DC_IRQ_SOURCE_HPD3RX;
case DCN_1_0__CTXID__DC_HPD4_RX_INT:
return DC_IRQ_SOURCE_HPD4RX;
case DCN_1_0__CTXID__DC_HPD5_RX_INT:
return DC_IRQ_SOURCE_HPD5RX;
case DCN_1_0__CTXID__DC_HPD6_RX_INT:
return DC_IRQ_SOURCE_HPD6RX;
default:
return DC_IRQ_SOURCE_INVALID;
}
break;
default:
return DC_IRQ_SOURCE_INVALID;
}
}
static bool hpd_ack(
struct irq_service *irq_service,
const struct irq_source_info *info)
{
uint32_t addr = info->status_reg;
uint32_t value = dm_read_reg(irq_service->ctx, addr);
uint32_t current_status =
get_reg_field_value(
value,
HPD0_DC_HPD_INT_STATUS,
DC_HPD_SENSE_DELAYED);
dal_irq_service_ack_generic(irq_service, info);
value = dm_read_reg(irq_service->ctx, info->enable_reg);
set_reg_field_value(
value,
current_status ? 0 : 1,
HPD0_DC_HPD_INT_CONTROL,
DC_HPD_INT_POLARITY);
dm_write_reg(irq_service->ctx, info->enable_reg, value);
return true;
}
static const struct irq_source_info_funcs hpd_irq_info_funcs = {
.set = NULL,
.ack = hpd_ack
};
static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
.set = NULL,
.ack = NULL
};
static const struct irq_source_info_funcs pflip_irq_info_funcs = {
.set = NULL,
.ack = NULL
};
static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
.set = NULL,
.ack = NULL
};
static const struct irq_source_info_funcs vblank_irq_info_funcs = {
.set = NULL,
.ack = NULL
};
static const struct irq_source_info_funcs outbox_irq_info_funcs = {
.set = NULL,
.ack = NULL
};
static const struct irq_source_info_funcs vline0_irq_info_funcs = {
.set = NULL,
.ack = NULL
};
#undef BASE_INNER
#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
/* compile time expand base address. */
#define BASE(seg) \
BASE_INNER(seg)
#define SRI(reg_name, block, id)\
BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
reg ## block ## id ## _ ## reg_name
#define SRI_DMUB(reg_name)\
BASE(reg ## reg_name ## _BASE_IDX) + \
reg ## reg_name
#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
.enable_reg = SRI(reg1, block, reg_num),\
.enable_mask = \
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
.enable_value = {\
block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
},\
.ack_reg = SRI(reg2, block, reg_num),\
.ack_mask = \
block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
.ack_value = \
block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
#define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
.enable_reg = SRI_DMUB(reg1),\
.enable_mask = \
reg1 ## __ ## mask1 ## _MASK,\
.enable_value = {\
reg1 ## __ ## mask1 ## _MASK,\
~reg1 ## __ ## mask1 ## _MASK \
},\
.ack_reg = SRI_DMUB(reg2),\
.ack_mask = \
reg2 ## __ ## mask2 ## _MASK,\
.ack_value = \
reg2 ## __ ## mask2 ## _MASK \
#define hpd_int_entry(reg_num)\
[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
IRQ_REG_ENTRY(HPD, reg_num,\
DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
.funcs = &hpd_irq_info_funcs\
}
#define hpd_rx_int_entry(reg_num)\
[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
IRQ_REG_ENTRY(HPD, reg_num,\
DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
.funcs = &hpd_rx_irq_info_funcs\
}
#define pflip_int_entry(reg_num)\
[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
IRQ_REG_ENTRY(HUBPREQ, reg_num,\
DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
.funcs = &pflip_irq_info_funcs\
}
/* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
* of DCE's DC_IRQ_SOURCE_VUPDATEx.
*/
#define vupdate_no_lock_int_entry(reg_num)\
[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
IRQ_REG_ENTRY(OTG, reg_num,\
OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
.funcs = &vupdate_no_lock_irq_info_funcs\
}
#define vblank_int_entry(reg_num)\
[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
IRQ_REG_ENTRY(OTG, reg_num,\
OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
.funcs = &vblank_irq_info_funcs\
}
#define vline0_int_entry(reg_num)\
[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
IRQ_REG_ENTRY(OTG, reg_num,\
OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
.funcs = &vline0_irq_info_funcs\
}
#define dmub_outbox_int_entry()\
[DC_IRQ_SOURCE_DMCUB_OUTBOX] = {\
IRQ_REG_ENTRY_DMUB(\
DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX1_READY_INT_EN,\
DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX1_READY_INT_ACK),\
.funcs = &outbox_irq_info_funcs\
}
#define dummy_irq_entry() \
{\
.funcs = &dummy_irq_info_funcs\
}
#define i2c_int_entry(reg_num) \
[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
#define dp_sink_int_entry(reg_num) \
[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
#define gpio_pad_int_entry(reg_num) \
[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
#define dc_underflow_int_entry(reg_num) \
[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
static const struct irq_source_info_funcs dummy_irq_info_funcs = {
.set = dal_irq_service_dummy_set,
.ack = dal_irq_service_dummy_ack
};
static const struct irq_source_info
irq_source_info_dcn315[DAL_IRQ_SOURCES_NUMBER] = {
[DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
hpd_int_entry(0),
hpd_int_entry(1),
hpd_int_entry(2),
hpd_int_entry(3),
hpd_int_entry(4),
hpd_rx_int_entry(0),
hpd_rx_int_entry(1),
hpd_rx_int_entry(2),
hpd_rx_int_entry(3),
hpd_rx_int_entry(4),
i2c_int_entry(1),
i2c_int_entry(2),
i2c_int_entry(3),
i2c_int_entry(4),
i2c_int_entry(5),
i2c_int_entry(6),
dp_sink_int_entry(1),
dp_sink_int_entry(2),
dp_sink_int_entry(3),
dp_sink_int_entry(4),
dp_sink_int_entry(5),
dp_sink_int_entry(6),
[DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
pflip_int_entry(0),
pflip_int_entry(1),
pflip_int_entry(2),
pflip_int_entry(3),
[DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
[DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
gpio_pad_int_entry(0),
gpio_pad_int_entry(1),
gpio_pad_int_entry(2),
gpio_pad_int_entry(3),
gpio_pad_int_entry(4),
gpio_pad_int_entry(5),
gpio_pad_int_entry(6),
gpio_pad_int_entry(7),
gpio_pad_int_entry(8),
gpio_pad_int_entry(9),
gpio_pad_int_entry(10),
gpio_pad_int_entry(11),
gpio_pad_int_entry(12),
gpio_pad_int_entry(13),
gpio_pad_int_entry(14),
gpio_pad_int_entry(15),
gpio_pad_int_entry(16),
gpio_pad_int_entry(17),
gpio_pad_int_entry(18),
gpio_pad_int_entry(19),
gpio_pad_int_entry(20),
gpio_pad_int_entry(21),
gpio_pad_int_entry(22),
gpio_pad_int_entry(23),
gpio_pad_int_entry(24),
gpio_pad_int_entry(25),
gpio_pad_int_entry(26),
gpio_pad_int_entry(27),
gpio_pad_int_entry(28),
gpio_pad_int_entry(29),
gpio_pad_int_entry(30),
dc_underflow_int_entry(1),
dc_underflow_int_entry(2),
dc_underflow_int_entry(3),
dc_underflow_int_entry(4),
dc_underflow_int_entry(5),
dc_underflow_int_entry(6),
[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
vupdate_no_lock_int_entry(0),
vupdate_no_lock_int_entry(1),
vupdate_no_lock_int_entry(2),
vupdate_no_lock_int_entry(3),
vblank_int_entry(0),
vblank_int_entry(1),
vblank_int_entry(2),
vblank_int_entry(3),
vline0_int_entry(0),
vline0_int_entry(1),
vline0_int_entry(2),
vline0_int_entry(3),
[DC_IRQ_SOURCE_DC5_VLINE1] = dummy_irq_entry(),
[DC_IRQ_SOURCE_DC6_VLINE1] = dummy_irq_entry(),
dmub_outbox_int_entry(),
};
static const struct irq_service_funcs irq_service_funcs_dcn315 = {
.to_dal_irq_source = to_dal_irq_source_dcn315
};
static void dcn315_irq_construct(
struct irq_service *irq_service,
struct irq_service_init_data *init_data)
{
dal_irq_service_construct(irq_service, init_data);
irq_service->info = irq_source_info_dcn315;
irq_service->funcs = &irq_service_funcs_dcn315;
}
struct irq_service *dal_irq_service_dcn315_create(
struct irq_service_init_data *init_data)
{
struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
GFP_KERNEL);
if (!irq_service)
return NULL;
dcn315_irq_construct(irq_service, init_data);
return irq_service;
}

34
drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.h Normal file
View File

@ -0,0 +1,34 @@
/*
* Copyright 2021 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_IRQ_SERVICE_DCN315_H__
#define __DAL_IRQ_SERVICE_DCN315_H__
#include "../irq_service.h"
struct irq_service *dal_irq_service_dcn315_create(
struct irq_service_init_data *init_data);
#endif /* __DAL_IRQ_SERVICE_DCN315_H__ */

1
drivers/gpu/drm/amd/display/dmub/dmub_srv.h
View File

@ -98,6 +98,7 @@ enum dmub_asic {
DMUB_ASIC_DCN303,
DMUB_ASIC_DCN31,
DMUB_ASIC_DCN31B,
DMUB_ASIC_DCN315,
DMUB_ASIC_DCN316,
DMUB_ASIC_MAX,
};

44
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
View File

@ -667,6 +667,10 @@ enum dmub_cmd_type {
* Command type used for EDID CEA parsing
*/
DMUB_CMD__EDID_CEA = 79,
/**
* Command type used for getting usbc cable ID
*/
DMUB_CMD_GET_USBC_CABLE_ID = 81,
/**
* Command type used for all VBIOS interface commands.
*/
@ -2483,6 +2487,38 @@ struct dmub_rb_cmd_edid_cea {
};
/**
* struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command.
*/
struct dmub_cmd_cable_id_input {
uint8_t phy_inst; /**< phy inst for cable id data */
};
/**
* struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command.
*/
struct dmub_cmd_cable_id_output {
uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */
uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */
uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */
uint8_t RESERVED :2; /**< reserved means not defined */
};
/**
* Definition of a DMUB_CMD_GET_USBC_CABLE_ID command
*/
struct dmub_rb_cmd_get_usbc_cable_id {
struct dmub_cmd_header header; /**< Command header */
/**
* Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command.
*/
union dmub_cmd_cable_id_data {
struct dmub_cmd_cable_id_input input; /**< Input */
struct dmub_cmd_cable_id_output output; /**< Output */
uint8_t output_raw; /**< Raw data output */
} data;
};
/**
* union dmub_rb_cmd - DMUB inbox command.
*/
@ -2648,6 +2684,10 @@ union dmub_rb_cmd {
* Definition of a DMUB_CMD__EDID_CEA command.
*/
struct dmub_rb_cmd_edid_cea edid_cea;
/**
* Definition of a DMUB_CMD_GET_USBC_CABLE_ID command.
*/
struct dmub_rb_cmd_get_usbc_cable_id cable_id;
};
/**
@ -2921,6 +2961,10 @@ static inline void dmub_rb_flush_pending(const struct dmub_rb *rb)
uint64_t temp;
uint8_t i;
/* Don't remove this.
* The contents need to actually be read from the ring buffer
* for this function to be effective.
*/
for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
temp = *data++;

4
drivers/gpu/drm/amd/display/dmub/src/Makefile
View File

@ -22,9 +22,7 @@
DMUB = dmub_srv.o dmub_srv_stat.o dmub_reg.o dmub_dcn20.o dmub_dcn21.o
DMUB += dmub_dcn30.o dmub_dcn301.o dmub_dcn302.o dmub_dcn303.o
DMUB += dmub_dcn31.o
DMUB += dmub_dcn316.o
DMUB += dmub_dcn31.o dmub_dcn315.o dmub_dcn316.o
AMD_DAL_DMUB = $(addprefix $(AMDDALPATH)/dmub/src/,$(DMUB))

62
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn315.c Normal file
View File

@ -0,0 +1,62 @@
/*
* Copyright 2021 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include "../dmub_srv.h"
#include "dmub_reg.h"
#include "dmub_dcn315.h"
#include "dcn/dcn_3_1_5_offset.h"
#include "dcn/dcn_3_1_5_sh_mask.h"
#define DCN_BASE__INST0_SEG0 0x00000012
#define DCN_BASE__INST0_SEG1 0x000000C0
#define DCN_BASE__INST0_SEG2 0x000034C0
#define DCN_BASE__INST0_SEG3 0x00009000
#define DCN_BASE__INST0_SEG4 0x02403C00
#define DCN_BASE__INST0_SEG5 0
#define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg
#define CTX dmub
#define REGS dmub->regs_dcn31
#define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
/* Registers. */
const struct dmub_srv_dcn31_regs dmub_srv_dcn315_regs = {
#define DMUB_SR(reg) REG_OFFSET_EXP(reg),
{
DMUB_DCN31_REGS()
DMCUB_INTERNAL_REGS()
},
#undef DMUB_SR
#define DMUB_SF(reg, field) FD_MASK(reg, field),
{ DMUB_DCN315_FIELDS() },
#undef DMUB_SF
#define DMUB_SF(reg, field) FD_SHIFT(reg, field),
{ DMUB_DCN315_FIELDS() },
#undef DMUB_SF
};

68
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn315.h Normal file
View File

@ -0,0 +1,68 @@
/*
* Copyright 2021 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef _DMUB_DCN315_H_
#define _DMUB_DCN315_H_
#include "dmub_dcn31.h"
#define DMUB_DCN315_FIELDS() \
DMUB_SF(DMCUB_CNTL, DMCUB_ENABLE) \
DMUB_SF(DMCUB_CNTL, DMCUB_TRACEPORT_EN) \
DMUB_SF(DMCUB_CNTL2, DMCUB_SOFT_RESET) \
DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET) \
DMUB_SF(DMCUB_SEC_CNTL, DMCUB_MEM_UNIT_ID) \
DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS) \
DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_TOP_ADDRESS) \
DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE) \
DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_TOP_ADDRESS) \
DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_ENABLE) \
DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_TOP_ADDRESS) \
DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_ENABLE) \
DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_TOP_ADDRESS) \
DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_ENABLE) \
DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_TOP_ADDRESS) \
DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_ENABLE) \
DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_TOP_ADDRESS) \
DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_ENABLE) \
DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_TOP_ADDRESS) \
DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE) \
DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_TOP_ADDRESS) \
DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_ENABLE) \
DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_TOP_ADDRESS) \
DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_ENABLE) \
DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_TOP_ADDRESS) \
DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_ENABLE) \
DMUB_SF(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE) \
DMUB_SF(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET) \
DMUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE) \
DMUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET) \
DMUB_SF(DMCUB_INBOX0_WPTR, DMCUB_INBOX0_WPTR) \
DMUB_SF(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT2_INT_EN) \
DMUB_SF(DMCUB_INTERRUPT_ACK, DMCUB_GPINT2_INT_ACK)
extern const struct dmub_srv_dcn31_regs dmub_srv_dcn315_regs;
#endif /* _DMUB_DCN315_H_ */

9
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
View File

@ -32,6 +32,7 @@
#include "dmub_dcn302.h"
#include "dmub_dcn303.h"
#include "dmub_dcn31.h"
#include "dmub_dcn315.h"
#include "dmub_dcn316.h"
#include "os_types.h"
/*
@ -221,10 +222,14 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
case DMUB_ASIC_DCN31:
case DMUB_ASIC_DCN31B:
case DMUB_ASIC_DCN315:
case DMUB_ASIC_DCN316:
dmub->regs_dcn31 = &dmub_srv_dcn31_regs;
if (asic == DMUB_ASIC_DCN316)
if (asic == DMUB_ASIC_DCN315)
dmub->regs_dcn31 = &dmub_srv_dcn315_regs;
else if (asic == DMUB_ASIC_DCN316)
dmub->regs_dcn31 = &dmub_srv_dcn316_regs;
else
dmub->regs_dcn31 = &dmub_srv_dcn31_regs;
funcs->reset = dmub_dcn31_reset;
funcs->reset_release = dmub_dcn31_reset_release;
funcs->backdoor_load = dmub_dcn31_backdoor_load;

6
drivers/gpu/drm/amd/display/include/dal_asic_id.h
View File

@ -235,6 +235,12 @@ enum {
#define ASICREV_IS_YELLOW_CARP(eChipRev) ((eChipRev >= YELLOW_CARP_A0) && (eChipRev < YELLOW_CARP_UNKNOWN))
#endif
#define AMDGPU_FAMILY_GC_10_3_6 149
#define GC_10_3_6_A0 0x01
#define GC_10_3_6_UNKNOWN 0xFF
#define ASICREV_IS_GC_10_3_6(eChipRev) ((eChipRev >= GC_10_3_6_A0) && (eChipRev < GC_10_3_6_UNKNOWN))
#define AMDGPU_FAMILY_GC_10_3_7 151
#define GC_10_3_7_A0 0x01
#define GC_10_3_7_UNKNOWN 0xFF

1
drivers/gpu/drm/amd/display/include/dal_types.h
View File

@ -57,6 +57,7 @@ enum dce_version {
DCN_VERSION_3_02,
DCN_VERSION_3_03,
DCN_VERSION_3_1,
DCN_VERSION_3_15,
DCN_VERSION_3_16,
DCN_VERSION_MAX
};

1
drivers/gpu/drm/amd/display/include/ddc_service_types.h
View File

@ -34,6 +34,7 @@
#define DP_BRANCH_DEVICE_ID_90CC24 0x90CC24
#define DP_BRANCH_DEVICE_ID_00E04C 0x00E04C
#define DP_BRANCH_DEVICE_ID_006037 0x006037
#define DP_BRANCH_DEVICE_ID_001CF8 0x001CF8
#define DP_BRANCH_HW_REV_10 0x10
#define DP_BRANCH_HW_REV_20 0x20

15191
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_offset.h Normal file
View File

File diff suppressed because it is too large Load Diff

62061
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_sh_mask.h Normal file
View File

File diff suppressed because it is too large Load Diff

11957
drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_2_2_offset.h Normal file
View File

File diff suppressed because it is too large Load Diff

103633
drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_2_2_sh_mask.h Normal file
View File

File diff suppressed because it is too large Load Diff

2
drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h
View File

@ -104,6 +104,7 @@
#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5
#define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x6
#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb
#define HDP_MISC_CNTL__READ_BUFFER_WATERMARK__SHIFT 0xe
#define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15
#define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY__SHIFT 0x17
#define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE__SHIFT 0x18
@ -118,6 +119,7 @@
#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x00000020L
#define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x00000040L
#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x00000800L
#define HDP_MISC_CNTL__READ_BUFFER_WATERMARK_MASK 0x0000c000L
#define HDP_MISC_CNTL__FED_ENABLE_MASK 0x00200000L
#define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY_MASK 0x00800000L
#define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE_MASK 0x01000000L

455
drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_5_offset.h Normal file
View File

@ -0,0 +1,455 @@
/*
* Copyright 2022 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*
*/
#ifndef _mp_13_0_5_OFFSET_HEADER
#define _mp_13_0_5_OFFSET_HEADER
// addressBlock: mp_SmuMp0_SmnDec
// base address: 0x0
#define regMP0_SMN_C2PMSG_32 0x0060
#define regMP0_SMN_C2PMSG_32_BASE_IDX 0
#define regMP0_SMN_C2PMSG_33 0x0061
#define regMP0_SMN_C2PMSG_33_BASE_IDX 0
#define regMP0_SMN_C2PMSG_34 0x0062
#define regMP0_SMN_C2PMSG_34_BASE_IDX 0
#define regMP0_SMN_C2PMSG_35 0x0063
#define regMP0_SMN_C2PMSG_35_BASE_IDX 0
#define regMP0_SMN_C2PMSG_36 0x0064
#define regMP0_SMN_C2PMSG_36_BASE_IDX 0
#define regMP0_SMN_C2PMSG_37 0x0065
#define regMP0_SMN_C2PMSG_37_BASE_IDX 0
#define regMP0_SMN_C2PMSG_38 0x0066
#define regMP0_SMN_C2PMSG_38_BASE_IDX 0
#define regMP0_SMN_C2PMSG_39 0x0067
#define regMP0_SMN_C2PMSG_39_BASE_IDX 0
#define regMP0_SMN_C2PMSG_40 0x0068
#define regMP0_SMN_C2PMSG_40_BASE_IDX 0
#define regMP0_SMN_C2PMSG_41 0x0069
#define regMP0_SMN_C2PMSG_41_BASE_IDX 0
#define regMP0_SMN_C2PMSG_42 0x006a
#define regMP0_SMN_C2PMSG_42_BASE_IDX 0
#define regMP0_SMN_C2PMSG_43 0x006b
#define regMP0_SMN_C2PMSG_43_BASE_IDX 0
#define regMP0_SMN_C2PMSG_44 0x006c
#define regMP0_SMN_C2PMSG_44_BASE_IDX 0
#define regMP0_SMN_C2PMSG_45 0x006d
#define regMP0_SMN_C2PMSG_45_BASE_IDX 0
#define regMP0_SMN_C2PMSG_46 0x006e
#define regMP0_SMN_C2PMSG_46_BASE_IDX 0
#define regMP0_SMN_C2PMSG_47 0x006f
#define regMP0_SMN_C2PMSG_47_BASE_IDX 0
#define regMP0_SMN_C2PMSG_48 0x0070
#define regMP0_SMN_C2PMSG_48_BASE_IDX 0
#define regMP0_SMN_C2PMSG_49 0x0071
#define regMP0_SMN_C2PMSG_49_BASE_IDX 0
#define regMP0_SMN_C2PMSG_50 0x0072
#define regMP0_SMN_C2PMSG_50_BASE_IDX 0
#define regMP0_SMN_C2PMSG_51 0x0073
#define regMP0_SMN_C2PMSG_51_BASE_IDX 0
#define regMP0_SMN_C2PMSG_52 0x0074
#define regMP0_SMN_C2PMSG_52_BASE_IDX 0
#define regMP0_SMN_C2PMSG_53 0x0075
#define regMP0_SMN_C2PMSG_53_BASE_IDX 0
#define regMP0_SMN_C2PMSG_54 0x0076
#define regMP0_SMN_C2PMSG_54_BASE_IDX 0
#define regMP0_SMN_C2PMSG_55 0x0077
#define regMP0_SMN_C2PMSG_55_BASE_IDX 0
#define regMP0_SMN_C2PMSG_56 0x0078
#define regMP0_SMN_C2PMSG_56_BASE_IDX 0
#define regMP0_SMN_C2PMSG_57 0x0079
#define regMP0_SMN_C2PMSG_57_BASE_IDX 0
#define regMP0_SMN_C2PMSG_58 0x007a
#define regMP0_SMN_C2PMSG_58_BASE_IDX 0
#define regMP0_SMN_C2PMSG_59 0x007b
#define regMP0_SMN_C2PMSG_59_BASE_IDX 0
#define regMP0_SMN_C2PMSG_60 0x007c
#define regMP0_SMN_C2PMSG_60_BASE_IDX 0
#define regMP0_SMN_C2PMSG_61 0x007d
#define regMP0_SMN_C2PMSG_61_BASE_IDX 0
#define regMP0_SMN_C2PMSG_62 0x007e
#define regMP0_SMN_C2PMSG_62_BASE_IDX 0
#define regMP0_SMN_C2PMSG_63 0x007f
#define regMP0_SMN_C2PMSG_63_BASE_IDX 0
#define regMP0_SMN_C2PMSG_64 0x0080
#define regMP0_SMN_C2PMSG_64_BASE_IDX 0
#define regMP0_SMN_C2PMSG_65 0x0081
#define regMP0_SMN_C2PMSG_65_BASE_IDX 0
#define regMP0_SMN_C2PMSG_66 0x0082
#define regMP0_SMN_C2PMSG_66_BASE_IDX 0
#define regMP0_SMN_C2PMSG_67 0x0083
#define regMP0_SMN_C2PMSG_67_BASE_IDX 0
#define regMP0_SMN_C2PMSG_68 0x0084
#define regMP0_SMN_C2PMSG_68_BASE_IDX 0
#define regMP0_SMN_C2PMSG_69 0x0085
#define regMP0_SMN_C2PMSG_69_BASE_IDX 0
#define regMP0_SMN_C2PMSG_70 0x0086
#define regMP0_SMN_C2PMSG_70_BASE_IDX 0
#define regMP0_SMN_C2PMSG_71 0x0087
#define regMP0_SMN_C2PMSG_71_BASE_IDX 0
#define regMP0_SMN_C2PMSG_72 0x0088
#define regMP0_SMN_C2PMSG_72_BASE_IDX 0
#define regMP0_SMN_C2PMSG_73 0x0089
#define regMP0_SMN_C2PMSG_73_BASE_IDX 0
#define regMP0_SMN_C2PMSG_74 0x008a
#define regMP0_SMN_C2PMSG_74_BASE_IDX 0
#define regMP0_SMN_C2PMSG_75 0x008b
#define regMP0_SMN_C2PMSG_75_BASE_IDX 0
#define regMP0_SMN_C2PMSG_76 0x008c
#define regMP0_SMN_C2PMSG_76_BASE_IDX 0
#define regMP0_SMN_C2PMSG_77 0x008d
#define regMP0_SMN_C2PMSG_77_BASE_IDX 0
#define regMP0_SMN_C2PMSG_78 0x008e
#define regMP0_SMN_C2PMSG_78_BASE_IDX 0
#define regMP0_SMN_C2PMSG_79 0x008f
#define regMP0_SMN_C2PMSG_79_BASE_IDX 0
#define regMP0_SMN_C2PMSG_80 0x0090
#define regMP0_SMN_C2PMSG_80_BASE_IDX 0
#define regMP0_SMN_C2PMSG_81 0x0091
#define regMP0_SMN_C2PMSG_81_BASE_IDX 0
#define regMP0_SMN_C2PMSG_82 0x0092
#define regMP0_SMN_C2PMSG_82_BASE_IDX 0
#define regMP0_SMN_C2PMSG_83 0x0093
#define regMP0_SMN_C2PMSG_83_BASE_IDX 0
#define regMP0_SMN_C2PMSG_84 0x0094
#define regMP0_SMN_C2PMSG_84_BASE_IDX 0
#define regMP0_SMN_C2PMSG_85 0x0095
#define regMP0_SMN_C2PMSG_85_BASE_IDX 0
#define regMP0_SMN_C2PMSG_86 0x0096
#define regMP0_SMN_C2PMSG_86_BASE_IDX 0
#define regMP0_SMN_C2PMSG_87 0x0097
#define regMP0_SMN_C2PMSG_87_BASE_IDX 0
#define regMP0_SMN_C2PMSG_88 0x0098
#define regMP0_SMN_C2PMSG_88_BASE_IDX 0
#define regMP0_SMN_C2PMSG_89 0x0099
#define regMP0_SMN_C2PMSG_89_BASE_IDX 0
#define regMP0_SMN_C2PMSG_90 0x009a
#define regMP0_SMN_C2PMSG_90_BASE_IDX 0
#define regMP0_SMN_C2PMSG_91 0x009b
#define regMP0_SMN_C2PMSG_91_BASE_IDX 0
#define regMP0_SMN_C2PMSG_92 0x009c
#define regMP0_SMN_C2PMSG_92_BASE_IDX 0
#define regMP0_SMN_C2PMSG_93 0x009d
#define regMP0_SMN_C2PMSG_93_BASE_IDX 0
#define regMP0_SMN_C2PMSG_94 0x009e
#define regMP0_SMN_C2PMSG_94_BASE_IDX 0
#define regMP0_SMN_C2PMSG_95 0x009f
#define regMP0_SMN_C2PMSG_95_BASE_IDX 0
#define regMP0_SMN_C2PMSG_96 0x00a0
#define regMP0_SMN_C2PMSG_96_BASE_IDX 0
#define regMP0_SMN_C2PMSG_97 0x00a1
#define regMP0_SMN_C2PMSG_97_BASE_IDX 0
#define regMP0_SMN_C2PMSG_98 0x00a2
#define regMP0_SMN_C2PMSG_98_BASE_IDX 0
#define regMP0_SMN_C2PMSG_99 0x00a3
#define regMP0_SMN_C2PMSG_99_BASE_IDX 0
#define regMP0_SMN_C2PMSG_100 0x00a4
#define regMP0_SMN_C2PMSG_100_BASE_IDX 0
#define regMP0_SMN_C2PMSG_101 0x00a5
#define regMP0_SMN_C2PMSG_101_BASE_IDX 0
#define regMP0_SMN_C2PMSG_102 0x00a6
#define regMP0_SMN_C2PMSG_102_BASE_IDX 0
#define regMP0_SMN_C2PMSG_103 0x00a7
#define regMP0_SMN_C2PMSG_103_BASE_IDX 0
#define regMP0_SMN_IH_CREDIT 0x00c1
#define regMP0_SMN_IH_CREDIT_BASE_IDX 0
#define regMP0_SMN_IH_SW_INT 0x00c2
#define regMP0_SMN_IH_SW_INT_BASE_IDX 0
#define regMP0_SMN_IH_SW_INT_CTRL 0x00c3
#define regMP0_SMN_IH_SW_INT_CTRL_BASE_IDX 0
// addressBlock: mp_SmuMp1_SmnDec
// base address: 0x0
#define regMP1_SMN_C2PMSG_32 0x0260
#define regMP1_SMN_C2PMSG_32_BASE_IDX 0
#define regMP1_SMN_C2PMSG_33 0x0261
#define regMP1_SMN_C2PMSG_33_BASE_IDX 0
#define regMP1_SMN_C2PMSG_34 0x0262
#define regMP1_SMN_C2PMSG_34_BASE_IDX 0
#define regMP1_SMN_C2PMSG_35 0x0263
#define regMP1_SMN_C2PMSG_35_BASE_IDX 0
#define regMP1_SMN_C2PMSG_36 0x0264
#define regMP1_SMN_C2PMSG_36_BASE_IDX 0
#define regMP1_SMN_C2PMSG_37 0x0265
#define regMP1_SMN_C2PMSG_37_BASE_IDX 0
#define regMP1_SMN_C2PMSG_38 0x0266
#define regMP1_SMN_C2PMSG_38_BASE_IDX 0
#define regMP1_SMN_C2PMSG_39 0x0267
#define regMP1_SMN_C2PMSG_39_BASE_IDX 0
#define regMP1_SMN_C2PMSG_40 0x0268
#define regMP1_SMN_C2PMSG_40_BASE_IDX 0
#define regMP1_SMN_C2PMSG_41 0x0269
#define regMP1_SMN_C2PMSG_41_BASE_IDX 0
#define regMP1_SMN_C2PMSG_42 0x026a
#define regMP1_SMN_C2PMSG_42_BASE_IDX 0
#define regMP1_SMN_C2PMSG_43 0x026b
#define regMP1_SMN_C2PMSG_43_BASE_IDX 0
#define regMP1_SMN_C2PMSG_44 0x026c
#define regMP1_SMN_C2PMSG_44_BASE_IDX 0
#define regMP1_SMN_C2PMSG_45 0x026d
#define regMP1_SMN_C2PMSG_45_BASE_IDX 0
#define regMP1_SMN_C2PMSG_46 0x026e
#define regMP1_SMN_C2PMSG_46_BASE_IDX 0
#define regMP1_SMN_C2PMSG_47 0x026f
#define regMP1_SMN_C2PMSG_47_BASE_IDX 0
#define regMP1_SMN_C2PMSG_48 0x0270
#define regMP1_SMN_C2PMSG_48_BASE_IDX 0
#define regMP1_SMN_C2PMSG_49 0x0271
#define regMP1_SMN_C2PMSG_49_BASE_IDX 0
#define regMP1_SMN_C2PMSG_50 0x0272
#define regMP1_SMN_C2PMSG_50_BASE_IDX 0
#define regMP1_SMN_C2PMSG_51 0x0273
#define regMP1_SMN_C2PMSG_51_BASE_IDX 0
#define regMP1_SMN_C2PMSG_52 0x0274
#define regMP1_SMN_C2PMSG_52_BASE_IDX 0
#define regMP1_SMN_C2PMSG_53 0x0275
#define regMP1_SMN_C2PMSG_53_BASE_IDX 0
#define regMP1_SMN_C2PMSG_54 0x0276
#define regMP1_SMN_C2PMSG_54_BASE_IDX 0
#define regMP1_SMN_C2PMSG_55 0x0277
#define regMP1_SMN_C2PMSG_55_BASE_IDX 0
#define regMP1_SMN_C2PMSG_56 0x0278
#define regMP1_SMN_C2PMSG_56_BASE_IDX 0
#define regMP1_SMN_C2PMSG_57 0x0279
#define regMP1_SMN_C2PMSG_57_BASE_IDX 0
#define regMP1_SMN_C2PMSG_58 0x027a
#define regMP1_SMN_C2PMSG_58_BASE_IDX 0
#define regMP1_SMN_C2PMSG_59 0x027b
#define regMP1_SMN_C2PMSG_59_BASE_IDX 0
#define regMP1_SMN_C2PMSG_60 0x027c
#define regMP1_SMN_C2PMSG_60_BASE_IDX 0
#define regMP1_SMN_C2PMSG_61 0x027d
#define regMP1_SMN_C2PMSG_61_BASE_IDX 0
#define regMP1_SMN_C2PMSG_62 0x027e
#define regMP1_SMN_C2PMSG_62_BASE_IDX 0
#define regMP1_SMN_C2PMSG_63 0x027f
#define regMP1_SMN_C2PMSG_63_BASE_IDX 0
#define regMP1_SMN_C2PMSG_64 0x0280
#define regMP1_SMN_C2PMSG_64_BASE_IDX 0
#define regMP1_SMN_C2PMSG_65 0x0281
#define regMP1_SMN_C2PMSG_65_BASE_IDX 0
#define regMP1_SMN_C2PMSG_66 0x0282
#define regMP1_SMN_C2PMSG_66_BASE_IDX 0
#define regMP1_SMN_C2PMSG_67 0x0283
#define regMP1_SMN_C2PMSG_67_BASE_IDX 0
#define regMP1_SMN_C2PMSG_68 0x0284
#define regMP1_SMN_C2PMSG_68_BASE_IDX 0
#define regMP1_SMN_C2PMSG_69 0x0285
#define regMP1_SMN_C2PMSG_69_BASE_IDX 0
#define regMP1_SMN_C2PMSG_70 0x0286
#define regMP1_SMN_C2PMSG_70_BASE_IDX 0
#define regMP1_SMN_C2PMSG_71 0x0287
#define regMP1_SMN_C2PMSG_71_BASE_IDX 0
#define regMP1_SMN_C2PMSG_72 0x0288
#define regMP1_SMN_C2PMSG_72_BASE_IDX 0
#define regMP1_SMN_C2PMSG_73 0x0289
#define regMP1_SMN_C2PMSG_73_BASE_IDX 0
#define regMP1_SMN_C2PMSG_74 0x028a
#define regMP1_SMN_C2PMSG_74_BASE_IDX 0
#define regMP1_SMN_C2PMSG_75 0x028b
#define regMP1_SMN_C2PMSG_75_BASE_IDX 0
#define regMP1_SMN_C2PMSG_76 0x028c
#define regMP1_SMN_C2PMSG_76_BASE_IDX 0
#define regMP1_SMN_C2PMSG_77 0x028d
#define regMP1_SMN_C2PMSG_77_BASE_IDX 0
#define regMP1_SMN_C2PMSG_78 0x028e
#define regMP1_SMN_C2PMSG_78_BASE_IDX 0
#define regMP1_SMN_C2PMSG_79 0x028f
#define regMP1_SMN_C2PMSG_79_BASE_IDX 0
#define regMP1_SMN_C2PMSG_80 0x0290
#define regMP1_SMN_C2PMSG_80_BASE_IDX 0
#define regMP1_SMN_C2PMSG_81 0x0291
#define regMP1_SMN_C2PMSG_81_BASE_IDX 0
#define regMP1_SMN_C2PMSG_82 0x0292
#define regMP1_SMN_C2PMSG_82_BASE_IDX 0
#define regMP1_SMN_C2PMSG_83 0x0293
#define regMP1_SMN_C2PMSG_83_BASE_IDX 0
#define regMP1_SMN_C2PMSG_84 0x0294
#define regMP1_SMN_C2PMSG_84_BASE_IDX 0
#define regMP1_SMN_C2PMSG_85 0x0295
#define regMP1_SMN_C2PMSG_85_BASE_IDX 0
#define regMP1_SMN_C2PMSG_86 0x0296
#define regMP1_SMN_C2PMSG_86_BASE_IDX 0
#define regMP1_SMN_C2PMSG_87 0x0297
#define regMP1_SMN_C2PMSG_87_BASE_IDX 0
#define regMP1_SMN_C2PMSG_88 0x0298
#define regMP1_SMN_C2PMSG_88_BASE_IDX 0
#define regMP1_SMN_C2PMSG_89 0x0299
#define regMP1_SMN_C2PMSG_89_BASE_IDX 0
#define regMP1_SMN_C2PMSG_90 0x029a
#define regMP1_SMN_C2PMSG_90_BASE_IDX 0
#define regMP1_SMN_C2PMSG_91 0x029b
#define regMP1_SMN_C2PMSG_91_BASE_IDX 0
#define regMP1_SMN_C2PMSG_92 0x029c
#define regMP1_SMN_C2PMSG_92_BASE_IDX 0
#define regMP1_SMN_C2PMSG_93 0x029d
#define regMP1_SMN_C2PMSG_93_BASE_IDX 0
#define regMP1_SMN_C2PMSG_94 0x029e
#define regMP1_SMN_C2PMSG_94_BASE_IDX 0
#define regMP1_SMN_C2PMSG_95 0x029f
#define regMP1_SMN_C2PMSG_95_BASE_IDX 0
#define regMP1_SMN_C2PMSG_96 0x02a0
#define regMP1_SMN_C2PMSG_96_BASE_IDX 0
#define regMP1_SMN_C2PMSG_97 0x02a1
#define regMP1_SMN_C2PMSG_97_BASE_IDX 0
#define regMP1_SMN_C2PMSG_98 0x02a2
#define regMP1_SMN_C2PMSG_98_BASE_IDX 0
#define regMP1_SMN_C2PMSG_99 0x02a3
#define regMP1_SMN_C2PMSG_99_BASE_IDX 0
#define regMP1_SMN_C2PMSG_100 0x02a4
#define regMP1_SMN_C2PMSG_100_BASE_IDX 0
#define regMP1_SMN_C2PMSG_101 0x02a5
#define regMP1_SMN_C2PMSG_101_BASE_IDX 0
#define regMP1_SMN_C2PMSG_102 0x02a6
#define regMP1_SMN_C2PMSG_102_BASE_IDX 0
#define regMP1_SMN_C2PMSG_103 0x02a7
#define regMP1_SMN_C2PMSG_103_BASE_IDX 0
#define regMP1_SMN_C2PMSG_104 0x02a8
#define regMP1_SMN_C2PMSG_104_BASE_IDX 0
#define regMP1_SMN_C2PMSG_105 0x02a9
#define regMP1_SMN_C2PMSG_105_BASE_IDX 0
#define regMP1_SMN_C2PMSG_106 0x02aa
#define regMP1_SMN_C2PMSG_106_BASE_IDX 0
#define regMP1_SMN_C2PMSG_107 0x02ab
#define regMP1_SMN_C2PMSG_107_BASE_IDX 0
#define regMP1_SMN_C2PMSG_108 0x02ac
#define regMP1_SMN_C2PMSG_108_BASE_IDX 0
#define regMP1_SMN_C2PMSG_109 0x02ad
#define regMP1_SMN_C2PMSG_109_BASE_IDX 0
#define regMP1_SMN_C2PMSG_110 0x02ae
#define regMP1_SMN_C2PMSG_110_BASE_IDX 0
#define regMP1_SMN_C2PMSG_111 0x02af
#define regMP1_SMN_C2PMSG_111_BASE_IDX 0
#define regMP1_SMN_C2PMSG_112 0x02b0
#define regMP1_SMN_C2PMSG_112_BASE_IDX 0
#define regMP1_SMN_C2PMSG_113 0x02b1
#define regMP1_SMN_C2PMSG_113_BASE_IDX 0
#define regMP1_SMN_C2PMSG_114 0x02b2
#define regMP1_SMN_C2PMSG_114_BASE_IDX 0
#define regMP1_SMN_C2PMSG_115 0x02b3
#define regMP1_SMN_C2PMSG_115_BASE_IDX 0
#define regMP1_SMN_C2PMSG_116 0x02b4
#define regMP1_SMN_C2PMSG_116_BASE_IDX 0
#define regMP1_SMN_C2PMSG_117 0x02b5
#define regMP1_SMN_C2PMSG_117_BASE_IDX 0
#define regMP1_SMN_C2PMSG_118 0x02b6
#define regMP1_SMN_C2PMSG_118_BASE_IDX 0
#define regMP1_SMN_C2PMSG_119 0x02b7
#define regMP1_SMN_C2PMSG_119_BASE_IDX 0
#define regMP1_SMN_C2PMSG_120 0x02b8
#define regMP1_SMN_C2PMSG_120_BASE_IDX 0
#define regMP1_SMN_C2PMSG_121 0x02b9
#define regMP1_SMN_C2PMSG_121_BASE_IDX 0
#define regMP1_SMN_C2PMSG_122 0x02ba
#define regMP1_SMN_C2PMSG_122_BASE_IDX 0
#define regMP1_SMN_C2PMSG_123 0x02bb
#define regMP1_SMN_C2PMSG_123_BASE_IDX 0
#define regMP1_SMN_C2PMSG_124 0x02bc
#define regMP1_SMN_C2PMSG_124_BASE_IDX 0
#define regMP1_SMN_C2PMSG_125 0x02bd
#define regMP1_SMN_C2PMSG_125_BASE_IDX 0
#define regMP1_SMN_C2PMSG_126 0x02be
#define regMP1_SMN_C2PMSG_126_BASE_IDX 0
#define regMP1_SMN_C2PMSG_127 0x02bf
#define regMP1_SMN_C2PMSG_127_BASE_IDX 0
#define regMP1_SMN_IH_CREDIT 0x02c1
#define regMP1_SMN_IH_CREDIT_BASE_IDX 0
#define regMP1_SMN_IH_SW_INT 0x02c2
#define regMP1_SMN_IH_SW_INT_BASE_IDX 0
#define regMP1_SMN_IH_SW_INT_CTRL 0x02c3
#define regMP1_SMN_IH_SW_INT_CTRL_BASE_IDX 0
#define regMP1_SMN_FPS_CNT 0x02c4
#define regMP1_SMN_FPS_CNT_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH0 0x0340
#define regMP1_SMN_EXT_SCRATCH0_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH1 0x0341
#define regMP1_SMN_EXT_SCRATCH1_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH2 0x0342
#define regMP1_SMN_EXT_SCRATCH2_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH3 0x0343
#define regMP1_SMN_EXT_SCRATCH3_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH4 0x0344
#define regMP1_SMN_EXT_SCRATCH4_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH5 0x0345
#define regMP1_SMN_EXT_SCRATCH5_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH6 0x0346
#define regMP1_SMN_EXT_SCRATCH6_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH7 0x0347
#define regMP1_SMN_EXT_SCRATCH7_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH8 0x0348
#define regMP1_SMN_EXT_SCRATCH8_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH10 0x034a
#define regMP1_SMN_EXT_SCRATCH10_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH11 0x034b
#define regMP1_SMN_EXT_SCRATCH11_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH12 0x034c
#define regMP1_SMN_EXT_SCRATCH12_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH13 0x034d
#define regMP1_SMN_EXT_SCRATCH13_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH14 0x034e
#define regMP1_SMN_EXT_SCRATCH14_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH15 0x034f
#define regMP1_SMN_EXT_SCRATCH15_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH16 0x0350
#define regMP1_SMN_EXT_SCRATCH16_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH17 0x0351
#define regMP1_SMN_EXT_SCRATCH17_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH18 0x0352
#define regMP1_SMN_EXT_SCRATCH18_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH19 0x0353
#define regMP1_SMN_EXT_SCRATCH19_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH20 0x0354
#define regMP1_SMN_EXT_SCRATCH20_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH21 0x0355
#define regMP1_SMN_EXT_SCRATCH21_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH22 0x0356
#define regMP1_SMN_EXT_SCRATCH22_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH23 0x0357
#define regMP1_SMN_EXT_SCRATCH23_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH24 0x0358
#define regMP1_SMN_EXT_SCRATCH24_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH25 0x0359
#define regMP1_SMN_EXT_SCRATCH25_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH26 0x035a
#define regMP1_SMN_EXT_SCRATCH26_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH27 0x035b
#define regMP1_SMN_EXT_SCRATCH27_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH28 0x035c
#define regMP1_SMN_EXT_SCRATCH28_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH29 0x035d
#define regMP1_SMN_EXT_SCRATCH29_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH30 0x035e
#define regMP1_SMN_EXT_SCRATCH30_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH31 0x035f
#define regMP1_SMN_EXT_SCRATCH31_BASE_IDX 0
// addressBlock: mp_SmuMp1Pub_CruDec
// base address: 0x0
#define regMP1_FIRMWARE_FLAGS 0xbee009
#define regMP1_FIRMWARE_FLAGS_BASE_IDX 0
#endif

672
drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_5_sh_mask.h Normal file
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@ -0,0 +1,672 @@
/*
* Copyright 2022 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*
*/
#ifndef _mp_13_0_5_SH_MASK_HEADER
#define _mp_13_0_5_SH_MASK_HEADER
// addressBlock: mp_SmuMp0_SmnDec
//MP0_SMN_C2PMSG_32
#define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_33
#define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_34
#define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_35
#define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_36
#define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_37
#define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_38
#define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_39
#define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_40
#define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_41
#define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_42
#define MP0_SMN_C2PMSG_42__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_43
#define MP0_SMN_C2PMSG_43__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_44
#define MP0_SMN_C2PMSG_44__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_45
#define MP0_SMN_C2PMSG_45__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_46
#define MP0_SMN_C2PMSG_46__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_47
#define MP0_SMN_C2PMSG_47__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_48
#define MP0_SMN_C2PMSG_48__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_49
#define MP0_SMN_C2PMSG_49__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_50
#define MP0_SMN_C2PMSG_50__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_51
#define MP0_SMN_C2PMSG_51__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_52
#define MP0_SMN_C2PMSG_52__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_53
#define MP0_SMN_C2PMSG_53__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_54
#define MP0_SMN_C2PMSG_54__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_55
#define MP0_SMN_C2PMSG_55__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_56
#define MP0_SMN_C2PMSG_56__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_57
#define MP0_SMN_C2PMSG_57__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_58
#define MP0_SMN_C2PMSG_58__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_59
#define MP0_SMN_C2PMSG_59__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_60
#define MP0_SMN_C2PMSG_60__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_61
#define MP0_SMN_C2PMSG_61__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_62
#define MP0_SMN_C2PMSG_62__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_63
#define MP0_SMN_C2PMSG_63__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_64
#define MP0_SMN_C2PMSG_64__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_65
#define MP0_SMN_C2PMSG_65__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_66
#define MP0_SMN_C2PMSG_66__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_67
#define MP0_SMN_C2PMSG_67__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_68
#define MP0_SMN_C2PMSG_68__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_69
#define MP0_SMN_C2PMSG_69__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_70
#define MP0_SMN_C2PMSG_70__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_71
#define MP0_SMN_C2PMSG_71__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_72
#define MP0_SMN_C2PMSG_72__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_73
#define MP0_SMN_C2PMSG_73__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_74
#define MP0_SMN_C2PMSG_74__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_75
#define MP0_SMN_C2PMSG_75__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_76
#define MP0_SMN_C2PMSG_76__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_77
#define MP0_SMN_C2PMSG_77__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_78
#define MP0_SMN_C2PMSG_78__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_79
#define MP0_SMN_C2PMSG_79__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_80
#define MP0_SMN_C2PMSG_80__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_81
#define MP0_SMN_C2PMSG_81__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_82
#define MP0_SMN_C2PMSG_82__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_83
#define MP0_SMN_C2PMSG_83__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_84
#define MP0_SMN_C2PMSG_84__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_85
#define MP0_SMN_C2PMSG_85__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_86
#define MP0_SMN_C2PMSG_86__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_87
#define MP0_SMN_C2PMSG_87__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_88
#define MP0_SMN_C2PMSG_88__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_89
#define MP0_SMN_C2PMSG_89__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_90
#define MP0_SMN_C2PMSG_90__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_91
#define MP0_SMN_C2PMSG_91__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_92
#define MP0_SMN_C2PMSG_92__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_93
#define MP0_SMN_C2PMSG_93__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_94
#define MP0_SMN_C2PMSG_94__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_95
#define MP0_SMN_C2PMSG_95__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_96
#define MP0_SMN_C2PMSG_96__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_97
#define MP0_SMN_C2PMSG_97__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_98
#define MP0_SMN_C2PMSG_98__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_99
#define MP0_SMN_C2PMSG_99__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_100
#define MP0_SMN_C2PMSG_100__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_101
#define MP0_SMN_C2PMSG_101__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_102
#define MP0_SMN_C2PMSG_102__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_C2PMSG_103
#define MP0_SMN_C2PMSG_103__CONTENT__SHIFT 0x0
#define MP0_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
//MP0_SMN_IH_CREDIT
#define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
#define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10
#define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
#define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
//MP0_SMN_IH_SW_INT
#define MP0_SMN_IH_SW_INT__ID__SHIFT 0x0
#define MP0_SMN_IH_SW_INT__VALID__SHIFT 0x8
#define MP0_SMN_IH_SW_INT__ID_MASK 0x000000FFL
#define MP0_SMN_IH_SW_INT__VALID_MASK 0x00000100L
//MP0_SMN_IH_SW_INT_CTRL
#define MP0_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0
#define MP0_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8
#define MP0_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L
#define MP0_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L
// addressBlock: mp_SmuMp1_SmnDec
//MP1_SMN_C2PMSG_32
#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_33
#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_34
#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_35
#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_36
#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_37
#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_38
#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_39
#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_40
#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_41
#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_42
#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_43
#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_44
#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_45
#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_46
#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_47
#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_48
#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_49
#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_50
#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_51
#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_52
#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_53
#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_54
#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_55
#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_56
#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_57
#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_58
#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_59
#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_60
#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_61
#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_62
#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_63
#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_64
#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_65
#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_66
#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_67
#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_68
#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_69
#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_70
#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_71
#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_72
#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_73
#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_74
#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_75
#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_76
#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_77
#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_78
#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_79
#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_80
#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_81
#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_82
#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_83
#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_84
#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_85
#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_86
#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_87
#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_88
#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_89
#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_90
#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_91
#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_92
#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_93
#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_94
#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_95
#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_96
#define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_97
#define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_98
#define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_99
#define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_100
#define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_101
#define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_102
#define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_103
#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_104
#define MP1_SMN_C2PMSG_104__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_104__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_105
#define MP1_SMN_C2PMSG_105__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_105__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_106
#define MP1_SMN_C2PMSG_106__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_106__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_107
#define MP1_SMN_C2PMSG_107__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_107__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_108
#define MP1_SMN_C2PMSG_108__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_108__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_109
#define MP1_SMN_C2PMSG_109__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_109__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_110
#define MP1_SMN_C2PMSG_110__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_110__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_111
#define MP1_SMN_C2PMSG_111__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_111__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_112
#define MP1_SMN_C2PMSG_112__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_112__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_113
#define MP1_SMN_C2PMSG_113__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_113__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_114
#define MP1_SMN_C2PMSG_114__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_114__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_115
#define MP1_SMN_C2PMSG_115__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_115__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_116
#define MP1_SMN_C2PMSG_116__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_116__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_117
#define MP1_SMN_C2PMSG_117__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_117__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_118
#define MP1_SMN_C2PMSG_118__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_118__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_119
#define MP1_SMN_C2PMSG_119__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_119__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_120
#define MP1_SMN_C2PMSG_120__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_120__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_121
#define MP1_SMN_C2PMSG_121__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_121__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_122
#define MP1_SMN_C2PMSG_122__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_122__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_123
#define MP1_SMN_C2PMSG_123__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_123__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_124
#define MP1_SMN_C2PMSG_124__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_124__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_125
#define MP1_SMN_C2PMSG_125__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_125__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_126
#define MP1_SMN_C2PMSG_126__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_126__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_127
#define MP1_SMN_C2PMSG_127__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_127__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_IH_CREDIT
#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10
#define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
#define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
//MP1_SMN_IH_SW_INT
#define MP1_SMN_IH_SW_INT__ID__SHIFT 0x0
#define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x8
#define MP1_SMN_IH_SW_INT__ID_MASK 0x000000FFL
#define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000100L
//MP1_SMN_IH_SW_INT_CTRL
#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0
#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8
#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L
#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L
//MP1_SMN_FPS_CNT
#define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0
#define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH0
#define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH1
#define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH2
#define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH3
#define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH4
#define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH5
#define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH6
#define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH7
#define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH8
#define MP1_SMN_EXT_SCRATCH8__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH8__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH10
#define MP1_SMN_EXT_SCRATCH10__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH10__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH11
#define MP1_SMN_EXT_SCRATCH11__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH11__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH12
#define MP1_SMN_EXT_SCRATCH12__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH12__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH13
#define MP1_SMN_EXT_SCRATCH13__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH13__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH14
#define MP1_SMN_EXT_SCRATCH14__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH14__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH15
#define MP1_SMN_EXT_SCRATCH15__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH15__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH16
#define MP1_SMN_EXT_SCRATCH16__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH16__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH17
#define MP1_SMN_EXT_SCRATCH17__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH17__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH18
#define MP1_SMN_EXT_SCRATCH18__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH18__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH19
#define MP1_SMN_EXT_SCRATCH19__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH19__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH20
#define MP1_SMN_EXT_SCRATCH20__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH20__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH21
#define MP1_SMN_EXT_SCRATCH21__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH21__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH22
#define MP1_SMN_EXT_SCRATCH22__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH22__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH23
#define MP1_SMN_EXT_SCRATCH23__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH23__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH24
#define MP1_SMN_EXT_SCRATCH24__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH24__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH25
#define MP1_SMN_EXT_SCRATCH25__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH25__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH26
#define MP1_SMN_EXT_SCRATCH26__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH26__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH27
#define MP1_SMN_EXT_SCRATCH27__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH27__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH28
#define MP1_SMN_EXT_SCRATCH28__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH28__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH29
#define MP1_SMN_EXT_SCRATCH29__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH29__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH30
#define MP1_SMN_EXT_SCRATCH30__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH30__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH31
#define MP1_SMN_EXT_SCRATCH31__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH31__DATA_MASK 0xFFFFFFFFL
// addressBlock: mp_SmuMp1Pub_CruDec
//MP1_FIRMWARE_FLAGS
#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0
#define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1
#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L
#define MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL
#endif

4
drivers/gpu/drm/amd/pm/amdgpu_pm.c
View File

@ -3182,6 +3182,10 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
return 0;
/* under pp one vf mode manage of hwmon attributes is not supported */
if (amdgpu_sriov_is_pp_one_vf(adev))
effective_mode &= ~S_IWUSR;
/* Skip fan attributes if fan is not present */
if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||

4
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
View File

@ -37,6 +37,7 @@
#include "aldebaran_ppt.h"
#include "yellow_carp_ppt.h"
#include "cyan_skillfish_ppt.h"
#include "smu_v13_0_5_ppt.h"
#include "amd_pcie.h"
/*
@ -535,6 +536,9 @@ static int smu_set_funcs(struct amdgpu_device *adev)
case IP_VERSION(13, 0, 8):
yellow_carp_set_ppt_funcs(smu);
break;
case IP_VERSION(13, 0, 5):
smu_v13_0_5_set_ppt_funcs(smu);
break;
case IP_VERSION(11, 0, 8):
cyan_skillfish_set_ppt_funcs(smu);
break;

140
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_5.h Normal file
View File

@ -0,0 +1,140 @@
/*
* Copyright 2020 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __SMU13_DRIVER_IF_V13_0_5_H__
#define __SMU13_DRIVER_IF_V13_0_5_H__
#define PMFW_DRIVER_IF_VERSION 4
// Throttler Status Bitmask
#define THROTTLER_STATUS_BIT_SPL 0
#define THROTTLER_STATUS_BIT_FPPT 1
#define THROTTLER_STATUS_BIT_SPPT 2
#define THROTTLER_STATUS_BIT_SPPT_APU 3
#define THROTTLER_STATUS_BIT_THM_CORE 4
#define THROTTLER_STATUS_BIT_THM_GFX 5
#define THROTTLER_STATUS_BIT_THM_SOC 6
#define THROTTLER_STATUS_BIT_TDC_VDD 7
#define THROTTLER_STATUS_BIT_TDC_SOC 8
#define THROTTLER_STATUS_BIT_PROCHOT_CPU 9
#define THROTTLER_STATUS_BIT_PROCHOT_GFX 10
#define THROTTLER_STATUS_BIT_EDC_CPU 11
#define THROTTLER_STATUS_BIT_EDC_GFX 12
#define NUM_DCFCLK_DPM_LEVELS 4
#define NUM_DISPCLK_DPM_LEVELS 4
#define NUM_DPPCLK_DPM_LEVELS 4
#define NUM_SOCCLK_DPM_LEVELS 4
#define NUM_VCN_DPM_LEVELS 4
#define NUM_SOC_VOLTAGE_LEVELS 4
#define NUM_DF_PSTATE_LEVELS 4
typedef struct {
uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
uint16_t MinMclk;
uint16_t MaxMclk;
uint8_t WmSetting;
uint8_t WmType; // Used for normal pstate change or memory retraining
uint8_t Padding[2];
} WatermarkRowGeneric_t;
#define NUM_WM_RANGES 4
#define WM_PSTATE_CHG 0
#define WM_RETRAINING 1
typedef enum {
WM_SOCCLK = 0,
WM_DCFCLK,
WM_COUNT,
} WM_CLOCK_e;
typedef struct {
// Watermarks
WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
uint32_t MmHubPadding[7]; // SMU internal use
} Watermarks_t;
typedef struct {
uint32_t FClk;
uint32_t MemClk;
uint32_t Voltage;
} DfPstateTable_t;
typedef struct {
uint16_t GfxclkFrequency; //[MHz]
uint16_t SocclkFrequency; //[MHz]
uint16_t VclkFrequency; //[MHz]
uint16_t DclkFrequency; //[MHz]
uint16_t MemclkFrequency; //[MHz]
uint16_t spare;
uint16_t GfxActivity; //[centi]
uint16_t UvdActivity; //[centi]
uint16_t Voltage[2]; //[mV] indices: VDDCR_VDD, VDDCR_SOC
uint16_t Current[2]; //[mA] indices: VDDCR_VDD, VDDCR_SOC
uint16_t Power[2]; //[mW] indices: VDDCR_VDD, VDDCR_SOC
uint16_t GfxTemperature; //[centi-Celsius]
uint16_t SocTemperature; //[centi-Celsius]
uint16_t ThrottlerStatus;
uint16_t CurrentSocketPower; //[mW]
uint16_t spare1;
} SmuMetrics_t;
//Freq in MHz
//Voltage in milli volts with 2 fractional bits
typedef struct {
uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];
uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
uint32_t VClocks[NUM_VCN_DPM_LEVELS];
uint32_t DClocks[NUM_VCN_DPM_LEVELS];
uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];
DfPstateTable_t DfPstateTable[NUM_DF_PSTATE_LEVELS];
uint8_t NumDcfClkLevelsEnabled;
uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk
uint8_t NumSocClkLevelsEnabled;
uint8_t VcnClkLevelsEnabled; //Applies to both Vclk and Dclk
uint8_t NumDfPstatesEnabled;
uint8_t spare[3];
uint32_t MinGfxClk;
uint32_t MaxGfxClk;
} DpmClocks_t;
#define TABLE_BIOS_IF 0 // Called by BIOS
#define TABLE_WATERMARKS 1 // Called by DAL through VBIOS
#define TABLE_CUSTOM_DPM 2 // Called by Driver
#define TABLE_SPARE1 3
#define TABLE_DPMCLOCKS 4 // Called by Driver and VBIOS
#define TABLE_MOMENTARY_PM 5 // Called by Tools
#define TABLE_MODERN_STDBY 6 // Called by Tools for Modern Standby Log
#define TABLE_SMU_METRICS 7 // Called by Driver
#define TABLE_COUNT 8
#endif

126
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_5_pmfw.h Normal file
View File

@ -0,0 +1,126 @@
/*
* Copyright 2020 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __SMU_V13_0_5_PMFW_H__
#define __SMU_V13_0_5_PMFW_H__
#include "smu13_driver_if_v13_0_5.h"
#pragma pack(push, 1)
#define ENABLE_DEBUG_FEATURES
// Firmware features
// Feature Control Defines
#define FEATURE_DATA_CALCULATION_BIT 0
#define FEATURE_PPT_BIT 1
#define FEATURE_TDC_BIT 2
#define FEATURE_THERMAL_BIT 3
#define FEATURE_FIT_BIT 4
#define FEATURE_EDC_BIT 5
#define FEATURE_CSTATE_BOOST_BIT 6
#define FEATURE_PROCHOT_BIT 7
#define FEATURE_CCLK_DPM_BIT 8
#define FEATURE_FCLK_DPM_BIT 9
#define FEATURE_LCLK_DPM_BIT 10
#define FEATURE_PSI7_BIT 11
#define FEATURE_DLDO_BIT 12
#define FEATURE_SOCCLK_DEEP_SLEEP_BIT 13
#define FEATURE_LCLK_DEEP_SLEEP_BIT 14
#define FEATURE_SHUBCLK_DEEP_SLEEP_BIT 15
#define FEATURE_DVO_BIT 16
#define FEATURE_CC6_BIT 17
#define FEATURE_PC6_BIT 18
#define FEATURE_DF_CSTATES_BIT 19
#define FEATURE_CLOCK_GATING_BIT 20
#define FEATURE_FAN_CONTROLLER_BIT 21
#define FEATURE_CPPC_BIT 22
#define FEATURE_DLDO_DROPOUT_LIMITER_BIT 23
#define FEATURE_CPPC_PREFERRED_CORES_BIT 24
#define FEATURE_GMI_FOLDING_BIT 25
#define FEATURE_GMI_DLWM_BIT 26
#define FEATURE_XGMI_DLWM_BIT 27
#define FEATURE_DF_LIGHT_CSTATE_BIT 28
#define FEATURE_SMNCLK_DEEP_SLEEP_BIT 29
#define FEATURE_PCIE_SPEED_CONTROLLER_BIT 30
#define FEATURE_GFX_DPM_BIT 31
#define FEATURE_DS_GFXCLK_BIT 32
#define FEATURE_PCC_BIT 33
#define FEATURE_spare0_BIT 34
#define FEATURE_S0I3_BIT 35
#define FEATURE_VCN_DPM_BIT 36
#define FEATURE_DS_VCN_BIT 37
#define FEATURE_MPDMA_TF_CLK_DEEP_SLEEP_BIT 38
#define FEATURE_MPDMA_PM_CLK_DEEP_SLEEP_BIT 39
#define FEATURE_VDDOFF_BIT 40
#define FEATURE_DCFCLK_DPM_BIT 41
#define FEATURE_DCFCLK_DEEP_SLEEP_BIT 42
#define FEATURE_ATHUB_PG_BIT 43
#define FEATURE_SOCCLK_DPM_BIT 44
#define FEATURE_SHUBCLK_DPM_BIT 45
#define FEATURE_MP0CLK_DPM_BIT 46
#define FEATURE_MP0CLK_DEEP_SLEEP_BIT 47
#define FEATURE_PERCCXPC6_BIT 48
#define FEATURE_GFXOFF_BIT 49
#define NUM_FEATURES 50
typedef struct {
// MP1_EXT_SCRATCH0
uint32_t CurrLevel_ACP : 4;
uint32_t CurrLevel_ISP : 4;
uint32_t CurrLevel_VCN : 4;
uint32_t CurrLevel_LCLK : 4;
uint32_t CurrLevel_MP0CLK : 4;
uint32_t CurrLevel_FCLK : 4;
uint32_t CurrLevel_SOCCLK : 4;
uint32_t CurrLevel_DCFCLK : 4;
// MP1_EXT_SCRATCH1
uint32_t TargLevel_ACP : 4;
uint32_t TargLevel_ISP : 4;
uint32_t TargLevel_VCN : 4;
uint32_t TargLevel_LCLK : 4;
uint32_t TargLevel_MP0CLK : 4;
uint32_t TargLevel_FCLK : 4;
uint32_t TargLevel_SOCCLK : 4;
uint32_t TargLevel_DCFCLK : 4;
// MP1_EXT_SCRATCH2
uint32_t CurrLevel_SHUBCLK : 4;
uint32_t TargLevel_SHUBCLK : 4;
uint32_t InUlv : 1;
uint32_t InS0i2 : 1;
uint32_t InWhisperMode : 1;
uint32_t GfxOn : 1;
uint32_t RsmuCalBusyDpmIndex: 8;
uint32_t DpmHandlerId : 8;
uint32_t DpmTimerId : 4;
// MP1_EXT_SCRATCH3
uint32_t ReadWriteSmnRegAddr: 32;
// MP1_EXT_SCRATCH4
uint32_t Reserved1;
// MP1_EXT_SCRATCH5
uint32_t FeatureStatus[NUM_FEATURES / 32];
} FwStatus_t;
#pragma pack(pop)
#endif

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