forked from Minki/linux
Thumb-2: Implement the unified arch/arm/mm support
This patch adds the ARM/Thumb-2 unified support to the arch/arm/mm/* files. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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b86040a59f
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347c8b70b1
@ -159,7 +159,9 @@ union offset_union {
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#define __get8_unaligned_check(ins,val,addr,err) \
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__asm__( \
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"1: "ins" %1, [%2], #1\n" \
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ARM( "1: "ins" %1, [%2], #1\n" ) \
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THUMB( "1: "ins" %1, [%2]\n" ) \
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THUMB( " add %2, %2, #1\n" ) \
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"2:\n" \
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" .section .fixup,\"ax\"\n" \
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" .align 2\n" \
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@ -215,7 +217,9 @@ union offset_union {
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do { \
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unsigned int err = 0, v = val, a = addr; \
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__asm__( FIRST_BYTE_16 \
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"1: "ins" %1, [%2], #1\n" \
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ARM( "1: "ins" %1, [%2], #1\n" ) \
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THUMB( "1: "ins" %1, [%2]\n" ) \
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THUMB( " add %2, %2, #1\n" ) \
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" mov %1, %1, "NEXT_BYTE"\n" \
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"2: "ins" %1, [%2]\n" \
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"3:\n" \
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@ -245,11 +249,17 @@ union offset_union {
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do { \
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unsigned int err = 0, v = val, a = addr; \
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__asm__( FIRST_BYTE_32 \
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"1: "ins" %1, [%2], #1\n" \
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ARM( "1: "ins" %1, [%2], #1\n" ) \
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THUMB( "1: "ins" %1, [%2]\n" ) \
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THUMB( " add %2, %2, #1\n" ) \
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" mov %1, %1, "NEXT_BYTE"\n" \
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"2: "ins" %1, [%2], #1\n" \
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ARM( "2: "ins" %1, [%2], #1\n" ) \
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THUMB( "2: "ins" %1, [%2]\n" ) \
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THUMB( " add %2, %2, #1\n" ) \
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" mov %1, %1, "NEXT_BYTE"\n" \
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"3: "ins" %1, [%2], #1\n" \
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ARM( "3: "ins" %1, [%2], #1\n" ) \
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THUMB( "3: "ins" %1, [%2]\n" ) \
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THUMB( " add %2, %2, #1\n" ) \
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" mov %1, %1, "NEXT_BYTE"\n" \
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"4: "ins" %1, [%2]\n" \
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"5:\n" \
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@ -21,7 +21,7 @@
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*
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* Flush the whole D-cache.
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*
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* Corrupted registers: r0-r5, r7, r9-r11
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* Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
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*
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* - mm - mm_struct describing address space
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*/
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@ -51,8 +51,12 @@ loop1:
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loop2:
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mov r9, r4 @ create working copy of max way size
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loop3:
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orr r11, r10, r9, lsl r5 @ factor way and cache number into r11
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orr r11, r11, r7, lsl r2 @ factor index number into r11
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ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11
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THUMB( lsl r6, r9, r5 )
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THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
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ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11
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THUMB( lsl r6, r7, r2 )
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THUMB( orr r11, r11, r6 ) @ factor index number into r11
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mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
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subs r9, r9, #1 @ decrement the way
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bge loop3
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@ -82,11 +86,13 @@ ENDPROC(v7_flush_dcache_all)
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*
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*/
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ENTRY(v7_flush_kern_cache_all)
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stmfd sp!, {r4-r5, r7, r9-r11, lr}
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ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} )
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THUMB( stmfd sp!, {r4-r7, r9-r11, lr} )
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bl v7_flush_dcache_all
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
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ldmfd sp!, {r4-r5, r7, r9-r11, lr}
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ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} )
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THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} )
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mov pc, lr
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ENDPROC(v7_flush_kern_cache_all)
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@ -127,7 +127,9 @@ ENDPROC(cpu_v7_switch_mm)
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*/
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ENTRY(cpu_v7_set_pte_ext)
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#ifdef CONFIG_MMU
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str r1, [r0], #-2048 @ linux version
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ARM( str r1, [r0], #-2048 ) @ linux version
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THUMB( str r1, [r0] ) @ linux version
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THUMB( sub r0, r0, #2048 )
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bic r3, r1, #0x000003f0
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bic r3, r3, #PTE_TYPE_MASK
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@ -273,6 +275,7 @@ __v7_setup:
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mrc p15, 0, r0, c1, c0, 0 @ read control register
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bic r0, r0, r5 @ clear bits them
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orr r0, r0, r6 @ set them
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THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
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mov pc, lr @ return to head.S:__ret
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ENDPROC(__v7_setup)
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