rtw89: 8852c: add chip_ops related to BTC
Add some chip_ops to support BT coexistence to work properly. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20220421120903.73715-15-pkshih@realtek.com
This commit is contained in:
Ping-Ke Shih
Kalle Valo
parent
f4ae7ccc2b
commit
2fb822f82a
@ -3048,11 +3048,18 @@
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#define B_AX_BT_CNT_RST_V1 BIT(1)
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#define B_AX_BT_CNT_EN BIT(0)
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#define R_BTC_BT_CNT_HIGH 0xDA14
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#define R_BTC_BT_CNT_LOW 0xDA18
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#define R_AX_BTC_FUNC_EN 0xDA20
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#define R_AX_BTC_FUNC_EN_C1 0xFA20
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#define B_AX_PTA_WL_TX_EN BIT(1)
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#define B_AX_PTA_EDCCA_EN BIT(0)
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#define R_BTC_COEX_WL_REQ 0xDA24
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#define B_BTC_TX_BCN_HI BIT(22)
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#define B_BTC_RSP_ACK_HI BIT(10)
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#define R_BTC_BREAK_TABLE 0xDA2C
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#define BTC_BREAK_PARAM 0xf0ffffff
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@ -2338,6 +2338,33 @@ static u8 rtw8852c_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_p
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return rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL);
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}
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static void rtw8852c_btc_set_rfe(struct rtw89_dev *rtwdev)
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{
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struct rtw89_btc *btc = &rtwdev->btc;
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struct rtw89_btc_module *module = &btc->mdinfo;
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module->rfe_type = rtwdev->efuse.rfe_type;
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module->cv = rtwdev->hal.cv;
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module->bt_solo = 0;
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module->switch_type = BTC_SWITCH_INTERNAL;
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if (module->rfe_type > 0)
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module->ant.num = (module->rfe_type % 2 ? 2 : 3);
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else
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module->ant.num = 2;
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module->ant.diversity = 0;
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module->ant.isolation = 10;
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if (module->ant.num == 3) {
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module->ant.type = BTC_ANT_DEDICATED;
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module->bt_pos = BTC_BT_ALONE;
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} else {
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module->ant.type = BTC_ANT_SHARED;
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module->bt_pos = BTC_BT_BTG;
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}
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}
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static void rtw8852c_ctrl_btg(struct rtw89_dev *rtwdev, bool btg)
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{
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if (btg) {
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@ -2440,6 +2467,159 @@ static void rtw8852c_btc_init_cfg(struct rtw89_dev *rtwdev)
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btc->cx.wl.status.map.init_ok = true;
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}
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static
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void rtw8852c_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state)
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{
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u32 bitmap = 0;
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u32 reg = 0;
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switch (map) {
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case BTC_PRI_MASK_TX_RESP:
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reg = R_BTC_COEX_WL_REQ;
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bitmap = B_BTC_RSP_ACK_HI;
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break;
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case BTC_PRI_MASK_BEACON:
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reg = R_BTC_COEX_WL_REQ;
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bitmap = B_BTC_TX_BCN_HI;
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break;
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default:
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return;
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}
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if (state)
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rtw89_write32_set(rtwdev, reg, bitmap);
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else
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rtw89_write32_clr(rtwdev, reg, bitmap);
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}
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union rtw8852c_btc_wl_txpwr_ctrl {
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u32 txpwr_val;
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struct {
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union {
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u16 ctrl_all_time;
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struct {
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s16 data:9;
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u16 rsvd:6;
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u16 flag:1;
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} all_time;
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};
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union {
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u16 ctrl_gnt_bt;
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struct {
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s16 data:9;
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u16 rsvd:7;
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} gnt_bt;
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};
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};
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} __packed;
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static void
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rtw8852c_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val)
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{
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union rtw8852c_btc_wl_txpwr_ctrl arg = { .txpwr_val = txpwr_val };
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s32 val;
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#define __write_ctrl(_reg, _msk, _val, _en, _cond) \
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do { \
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const typeof(_msk) __msk = _msk; \
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const typeof(_en) __en = _en; \
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u32 _wrt = FIELD_PREP(__msk, _val); \
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BUILD_BUG_ON((__msk & __en) != 0); \
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if (_cond) \
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_wrt |= __en; \
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else \
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_wrt &= ~__en; \
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rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \
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__msk | __en, _wrt); \
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} while (0)
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switch (arg.ctrl_all_time) {
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case 0xffff:
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val = 0;
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break;
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default:
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val = arg.all_time.data;
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break;
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}
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__write_ctrl(R_AX_PWR_RATE_CTRL, B_AX_FORCE_PWR_BY_RATE_VALUE_MASK,
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val, B_AX_FORCE_PWR_BY_RATE_EN,
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arg.ctrl_all_time != 0xffff);
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switch (arg.ctrl_gnt_bt) {
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case 0xffff:
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val = 0;
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break;
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default:
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val = arg.gnt_bt.data;
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break;
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};
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__write_ctrl(R_AX_PWR_COEXT_CTRL, B_AX_TXAGC_BT_MASK, val,
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B_AX_TXAGC_BT_EN, arg.ctrl_gnt_bt != 0xffff);
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#undef __write_ctrl
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}
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static
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s8 rtw8852c_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val)
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{
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return clamp_t(s8, val, -100, 0) + 100;
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}
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static
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void rtw8852c_btc_bt_aci_imp(struct rtw89_dev *rtwdev)
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{
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struct rtw89_btc *btc = &rtwdev->btc;
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struct rtw89_btc_dm *dm = &btc->dm;
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struct rtw89_btc_bt_info *bt = &btc->cx.bt;
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struct rtw89_btc_bt_link_info *b = &bt->link_info;
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/* fix LNA2 = level-5 for BT ACI issue at BTG */
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if (btc->dm.wl_btg_rx && b->profile_cnt.now != 0)
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dm->trx_para_level = 1;
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}
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static
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void rtw8852c_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
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{
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struct rtw89_btc *btc = &rtwdev->btc;
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struct rtw89_btc_cx *cx = &btc->cx;
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u32 val;
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val = rtw89_read32(rtwdev, R_BTC_BT_CNT_HIGH);
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cx->cnt_bt[BTC_BCNT_HIPRI_TX] = FIELD_GET(B_AX_STATIS_BT_HI_TX_MASK, val);
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cx->cnt_bt[BTC_BCNT_HIPRI_RX] = FIELD_GET(B_AX_STATIS_BT_HI_RX_MASK, val);
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val = rtw89_read32(rtwdev, R_BTC_BT_CNT_LOW);
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cx->cnt_bt[BTC_BCNT_LOPRI_TX] = FIELD_GET(B_AX_STATIS_BT_LO_TX_1_MASK, val);
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cx->cnt_bt[BTC_BCNT_LOPRI_RX] = FIELD_GET(B_AX_STATIS_BT_LO_RX_1_MASK, val);
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/* clock-gate off before reset counter*/
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rtw89_write32_set(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G);
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rtw89_write32_clr(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_RST);
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rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_RST);
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rtw89_write32_clr(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G);
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}
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static
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void rtw8852c_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state)
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{
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rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000);
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rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1);
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rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x620);
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/* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */
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if (state)
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rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0,
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RFREG_MASK, 0x179c);
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else
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rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0,
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RFREG_MASK, 0x208);
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rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
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}
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static void rtw8852c_fill_freq_with_ppdu(struct rtw89_dev *rtwdev,
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struct rtw89_rx_phy_ppdu *phy_ppdu,
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struct ieee80211_rx_status *status)
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@ -2546,7 +2726,14 @@ static const struct rtw89_chip_ops rtw8852c_chip_ops = {
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.resume_sch_tx = rtw89_mac_resume_sch_tx_v1,
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.h2c_dctl_sec_cam = rtw89_fw_h2c_dctl_sec_cam_v1,
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.btc_set_rfe = rtw8852c_btc_set_rfe,
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.btc_init_cfg = rtw8852c_btc_init_cfg,
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.btc_set_wl_pri = rtw8852c_btc_set_wl_pri,
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.btc_set_wl_txpwr_ctrl = rtw8852c_btc_set_wl_txpwr_ctrl,
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.btc_get_bt_rssi = rtw8852c_btc_get_bt_rssi,
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.btc_bt_aci_imp = rtw8852c_btc_bt_aci_imp,
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.btc_update_bt_cnt = rtw8852c_btc_update_bt_cnt,
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.btc_wl_s1_standby = rtw8852c_btc_wl_s1_standby,
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};
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const struct rtw89_chip_info rtw8852c_chip_info = {
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