forked from Minki/linux
gpio: fixes for v5.9-rc7
- fix uninitialized variable in gpio-pca953x - enable all 160 lines and fix interrupt configuration in gpio-aspeed-gpio - fix ast2600 bank properties in gpio-aspeed -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEFp3rbAvDxGAT0sefEacuoBRx13IFAl9t9MAACgkQEacuoBRx 13KaeA/5Aa9vY77HznP0i5G+SSJsndqiYiTpCbEpyywG16uy7d1/EKprwrM02Po6 79f06dz0ps3zHVmNjoVFJDIjKZ5qjNj8KTpWRqkgbNJLWVnbSAnMFlTPTv9xHM3D 23iRTHDVqC59RKvzksgNjsGvMov/hJrqKzSHbZFkE2gTQcngsKVWCvwAYMgiUr4O HE8lzGmp5zgA/LgwySwWxbhc0aDOKJpJ3FIW5IXYBf+3B5FVepiAfGIasIfi6pnc DT7960E3Bd6m6RGnH669w8sMwu5AWiA2rhsHOQQ1NN31ZB3WS2tOJikMEzb84D5H QOMugcULSgN081O9JwjZFHnvItIjsRT0sPDInVvKWstSOz4S15faSNRLU52FjKBu rfFlTeZJBHRh2qV6ymMVsomqM4cZ/1pPFApXzZtwpgOmj2CyJNLd3rORlz/bxEyc qvFog+tvpRn+tzmuSwkPmZafn0KwlHsbX7Ty5TNVRRWrTG6RueH75aB++CVvYUCi 5c+boe4ORe3HoSmr2CopWEhvS9ZzUbaTnkLQ/0KTduPiapeDuzujcoLrwVSSE3gk D/pbH5+KQGUhgeWLRNESGPWNrPpK5wu9OwWmDMtaYvipI73uMXeEqvJWzZdgyAsi 50DKcpXxVCYtNFLQ8ttxRFeYsCUYKl5THW+kqO/47AMvhYINk7o= =WVAS -----END PGP SIGNATURE----- Merge tag 'gpio-fixes-for-v5.9-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into fixes gpio: fixes for v5.9-rc7 - fix uninitialized variable in gpio-pca953x - enable all 160 lines and fix interrupt configuration in gpio-aspeed-gpio - fix ast2600 bank properties in gpio-aspeed
This commit is contained in:
Linus Walleij
commit
2e969d8a7f
@ -20,8 +20,9 @@ Required properties:
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- gpio-controller : Marks the device node as a GPIO controller
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- interrupts : Interrupt specifier, see interrupt-controller/interrupts.txt
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- interrupt-controller : Mark the GPIO controller as an interrupt-controller
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- ngpios : number of GPIO lines, see gpio.txt
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(should be multiple of 8, up to 80 pins)
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- ngpios : number of *hardware* GPIO lines, see gpio.txt. This will expose
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2 software GPIOs per hardware GPIO: one for hardware input, one for hardware
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output. Up to 80 pins, must be a multiple of 8.
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- clocks : A phandle to the APB clock for SGPM clock division
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- bus-frequency : SGPM CLK frequency
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@ -17,7 +17,17 @@
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#include <linux/spinlock.h>
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#include <linux/string.h>
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#define MAX_NR_SGPIO 80
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/*
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* MAX_NR_HW_GPIO represents the number of actual hardware-supported GPIOs (ie,
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* slots within the clocked serial GPIO data). Since each HW GPIO is both an
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* input and an output, we provide MAX_NR_HW_GPIO * 2 lines on our gpiochip
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* device.
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*
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* We use SGPIO_OUTPUT_OFFSET to define the split between the inputs and
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* outputs; the inputs start at line 0, the outputs start at OUTPUT_OFFSET.
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*/
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#define MAX_NR_HW_SGPIO 80
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#define SGPIO_OUTPUT_OFFSET MAX_NR_HW_SGPIO
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#define ASPEED_SGPIO_CTRL 0x54
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@ -30,8 +40,8 @@ struct aspeed_sgpio {
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struct clk *pclk;
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spinlock_t lock;
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void __iomem *base;
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uint32_t dir_in[3];
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int irq;
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int n_sgpio;
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};
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struct aspeed_sgpio_bank {
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@ -111,31 +121,69 @@ static void __iomem *bank_reg(struct aspeed_sgpio *gpio,
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}
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}
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#define GPIO_BANK(x) ((x) >> 5)
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#define GPIO_OFFSET(x) ((x) & 0x1f)
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#define GPIO_BANK(x) ((x % SGPIO_OUTPUT_OFFSET) >> 5)
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#define GPIO_OFFSET(x) ((x % SGPIO_OUTPUT_OFFSET) & 0x1f)
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#define GPIO_BIT(x) BIT(GPIO_OFFSET(x))
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static const struct aspeed_sgpio_bank *to_bank(unsigned int offset)
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{
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unsigned int bank = GPIO_BANK(offset);
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unsigned int bank;
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bank = GPIO_BANK(offset);
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WARN_ON(bank >= ARRAY_SIZE(aspeed_sgpio_banks));
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return &aspeed_sgpio_banks[bank];
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}
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static int aspeed_sgpio_init_valid_mask(struct gpio_chip *gc,
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unsigned long *valid_mask, unsigned int ngpios)
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{
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struct aspeed_sgpio *sgpio = gpiochip_get_data(gc);
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int n = sgpio->n_sgpio;
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int c = SGPIO_OUTPUT_OFFSET - n;
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WARN_ON(ngpios < MAX_NR_HW_SGPIO * 2);
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/* input GPIOs in the lower range */
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bitmap_set(valid_mask, 0, n);
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bitmap_clear(valid_mask, n, c);
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/* output GPIOS above SGPIO_OUTPUT_OFFSET */
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bitmap_set(valid_mask, SGPIO_OUTPUT_OFFSET, n);
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bitmap_clear(valid_mask, SGPIO_OUTPUT_OFFSET + n, c);
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return 0;
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}
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static void aspeed_sgpio_irq_init_valid_mask(struct gpio_chip *gc,
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unsigned long *valid_mask, unsigned int ngpios)
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{
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struct aspeed_sgpio *sgpio = gpiochip_get_data(gc);
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int n = sgpio->n_sgpio;
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WARN_ON(ngpios < MAX_NR_HW_SGPIO * 2);
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/* input GPIOs in the lower range */
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bitmap_set(valid_mask, 0, n);
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bitmap_clear(valid_mask, n, ngpios - n);
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}
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static bool aspeed_sgpio_is_input(unsigned int offset)
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{
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return offset < SGPIO_OUTPUT_OFFSET;
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}
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static int aspeed_sgpio_get(struct gpio_chip *gc, unsigned int offset)
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{
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struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
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const struct aspeed_sgpio_bank *bank = to_bank(offset);
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unsigned long flags;
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enum aspeed_sgpio_reg reg;
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bool is_input;
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int rc = 0;
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spin_lock_irqsave(&gpio->lock, flags);
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is_input = gpio->dir_in[GPIO_BANK(offset)] & GPIO_BIT(offset);
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reg = is_input ? reg_val : reg_rdata;
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reg = aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata;
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rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset));
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spin_unlock_irqrestore(&gpio->lock, flags);
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@ -143,22 +191,31 @@ static int aspeed_sgpio_get(struct gpio_chip *gc, unsigned int offset)
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return rc;
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}
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static void sgpio_set_value(struct gpio_chip *gc, unsigned int offset, int val)
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static int sgpio_set_value(struct gpio_chip *gc, unsigned int offset, int val)
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{
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struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
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const struct aspeed_sgpio_bank *bank = to_bank(offset);
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void __iomem *addr;
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void __iomem *addr_r, *addr_w;
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u32 reg = 0;
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addr = bank_reg(gpio, bank, reg_val);
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reg = ioread32(addr);
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if (aspeed_sgpio_is_input(offset))
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return -EINVAL;
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/* Since this is an output, read the cached value from rdata, then
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* update val. */
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addr_r = bank_reg(gpio, bank, reg_rdata);
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addr_w = bank_reg(gpio, bank, reg_val);
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reg = ioread32(addr_r);
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if (val)
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reg |= GPIO_BIT(offset);
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else
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reg &= ~GPIO_BIT(offset);
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iowrite32(reg, addr);
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iowrite32(reg, addr_w);
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return 0;
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}
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static void aspeed_sgpio_set(struct gpio_chip *gc, unsigned int offset, int val)
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@ -175,43 +232,28 @@ static void aspeed_sgpio_set(struct gpio_chip *gc, unsigned int offset, int val)
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static int aspeed_sgpio_dir_in(struct gpio_chip *gc, unsigned int offset)
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{
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struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
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unsigned long flags;
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spin_lock_irqsave(&gpio->lock, flags);
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gpio->dir_in[GPIO_BANK(offset)] |= GPIO_BIT(offset);
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spin_unlock_irqrestore(&gpio->lock, flags);
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return 0;
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return aspeed_sgpio_is_input(offset) ? 0 : -EINVAL;
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}
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static int aspeed_sgpio_dir_out(struct gpio_chip *gc, unsigned int offset, int val)
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{
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struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
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unsigned long flags;
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int rc;
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/* No special action is required for setting the direction; we'll
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* error-out in sgpio_set_value if this isn't an output GPIO */
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spin_lock_irqsave(&gpio->lock, flags);
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gpio->dir_in[GPIO_BANK(offset)] &= ~GPIO_BIT(offset);
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sgpio_set_value(gc, offset, val);
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rc = sgpio_set_value(gc, offset, val);
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spin_unlock_irqrestore(&gpio->lock, flags);
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return 0;
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return rc;
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}
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static int aspeed_sgpio_get_direction(struct gpio_chip *gc, unsigned int offset)
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{
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int dir_status;
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struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
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unsigned long flags;
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spin_lock_irqsave(&gpio->lock, flags);
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dir_status = gpio->dir_in[GPIO_BANK(offset)] & GPIO_BIT(offset);
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spin_unlock_irqrestore(&gpio->lock, flags);
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return dir_status;
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return !!aspeed_sgpio_is_input(offset);
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}
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static void irqd_to_aspeed_sgpio_data(struct irq_data *d,
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@ -402,6 +444,7 @@ static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,
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irq = &gpio->chip.irq;
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irq->chip = &aspeed_sgpio_irqchip;
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irq->init_valid_mask = aspeed_sgpio_irq_init_valid_mask;
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irq->handler = handle_bad_irq;
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irq->default_type = IRQ_TYPE_NONE;
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irq->parent_handler = aspeed_sgpio_irq_handler;
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@ -409,17 +452,15 @@ static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,
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irq->parents = &gpio->irq;
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irq->num_parents = 1;
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/* set IRQ settings and Enable Interrupt */
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/* Apply default IRQ settings */
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for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
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bank = &aspeed_sgpio_banks[i];
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/* set falling or level-low irq */
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iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type0));
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/* trigger type is edge */
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iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type1));
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/* dual edge trigger mode. */
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iowrite32(0xffffffff, bank_reg(gpio, bank, reg_irq_type2));
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/* enable irq */
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iowrite32(0xffffffff, bank_reg(gpio, bank, reg_irq_enable));
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/* single edge trigger */
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iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type2));
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}
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return 0;
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@ -452,11 +493,12 @@ static int __init aspeed_sgpio_probe(struct platform_device *pdev)
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if (rc < 0) {
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dev_err(&pdev->dev, "Could not read ngpios property\n");
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return -EINVAL;
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} else if (nr_gpios > MAX_NR_SGPIO) {
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} else if (nr_gpios > MAX_NR_HW_SGPIO) {
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dev_err(&pdev->dev, "Number of GPIOs exceeds the maximum of %d: %d\n",
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MAX_NR_SGPIO, nr_gpios);
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MAX_NR_HW_SGPIO, nr_gpios);
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return -EINVAL;
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}
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gpio->n_sgpio = nr_gpios;
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rc = of_property_read_u32(pdev->dev.of_node, "bus-frequency", &sgpio_freq);
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if (rc < 0) {
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@ -497,7 +539,8 @@ static int __init aspeed_sgpio_probe(struct platform_device *pdev)
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spin_lock_init(&gpio->lock);
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gpio->chip.parent = &pdev->dev;
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gpio->chip.ngpio = nr_gpios;
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gpio->chip.ngpio = MAX_NR_HW_SGPIO * 2;
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gpio->chip.init_valid_mask = aspeed_sgpio_init_valid_mask;
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gpio->chip.direction_input = aspeed_sgpio_dir_in;
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gpio->chip.direction_output = aspeed_sgpio_dir_out;
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gpio->chip.get_direction = aspeed_sgpio_get_direction;
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@ -509,9 +552,6 @@ static int __init aspeed_sgpio_probe(struct platform_device *pdev)
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gpio->chip.label = dev_name(&pdev->dev);
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gpio->chip.base = -1;
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/* set all SGPIO pins as input (1). */
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memset(gpio->dir_in, 0xff, sizeof(gpio->dir_in));
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aspeed_sgpio_setup_irqs(gpio, pdev);
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rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
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@ -1114,8 +1114,8 @@ static const struct aspeed_gpio_config ast2500_config =
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static const struct aspeed_bank_props ast2600_bank_props[] = {
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/* input output */
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{5, 0xffffffff, 0x0000ffff}, /* U/V/W/X */
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{6, 0xffff0000, 0x0fff0000}, /* Y/Z */
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{5, 0xffffffff, 0xffffff00}, /* U/V/W/X */
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{6, 0x0000ffff, 0x0000ffff}, /* Y/Z */
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{ },
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};
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@ -814,7 +814,7 @@ static irqreturn_t pca953x_irq_handler(int irq, void *devid)
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{
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struct pca953x_chip *chip = devid;
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struct gpio_chip *gc = &chip->gpio_chip;
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DECLARE_BITMAP(pending, MAX_LINE);
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DECLARE_BITMAP(pending, MAX_LINE) = {};
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int level;
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bool ret;
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