drm/amdgpu: move DC and PP shared data structures to dm_pp_interface.h
Move the display/power interfaces to one place. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rex Zhu
Alex Deucher
parent
4ff23be3d5
commit
2c2b67b479
@ -25,6 +25,145 @@
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#define PP_MAX_CLOCK_LEVELS 8
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enum amd_pp_display_config_type{
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AMD_PP_DisplayConfigType_None = 0,
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AMD_PP_DisplayConfigType_DP54 ,
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AMD_PP_DisplayConfigType_DP432 ,
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AMD_PP_DisplayConfigType_DP324 ,
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AMD_PP_DisplayConfigType_DP27,
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AMD_PP_DisplayConfigType_DP243,
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AMD_PP_DisplayConfigType_DP216,
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AMD_PP_DisplayConfigType_DP162,
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AMD_PP_DisplayConfigType_HDMI6G ,
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AMD_PP_DisplayConfigType_HDMI297 ,
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AMD_PP_DisplayConfigType_HDMI162,
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AMD_PP_DisplayConfigType_LVDS,
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AMD_PP_DisplayConfigType_DVI,
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AMD_PP_DisplayConfigType_WIRELESS,
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AMD_PP_DisplayConfigType_VGA
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};
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struct single_display_configuration
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{
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uint32_t controller_index;
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uint32_t controller_id;
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uint32_t signal_type;
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uint32_t display_state;
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/* phy id for the primary internal transmitter */
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uint8_t primary_transmitter_phyi_d;
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/* bitmap with the active lanes */
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uint8_t primary_transmitter_active_lanemap;
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/* phy id for the secondary internal transmitter (for dual-link dvi) */
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uint8_t secondary_transmitter_phy_id;
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/* bitmap with the active lanes */
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uint8_t secondary_transmitter_active_lanemap;
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/* misc phy settings for SMU. */
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uint32_t config_flags;
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uint32_t display_type;
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uint32_t view_resolution_cx;
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uint32_t view_resolution_cy;
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enum amd_pp_display_config_type displayconfigtype;
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uint32_t vertical_refresh; /* for active display */
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};
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#define MAX_NUM_DISPLAY 32
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struct amd_pp_display_configuration {
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bool nb_pstate_switch_disable;/* controls NB PState switch */
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bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
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bool cpu_pstate_disable;
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uint32_t cpu_pstate_separation_time;
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uint32_t num_display; /* total number of display*/
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uint32_t num_path_including_non_display;
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uint32_t crossfire_display_index;
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uint32_t min_mem_set_clock;
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uint32_t min_core_set_clock;
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/* unit 10KHz x bit*/
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uint32_t min_bus_bandwidth;
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/* minimum required stutter sclk, in 10khz uint32_t ulMinCoreSetClk;*/
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uint32_t min_core_set_clock_in_sr;
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struct single_display_configuration displays[MAX_NUM_DISPLAY];
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uint32_t vrefresh; /* for active display*/
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uint32_t min_vblank_time; /* for active display*/
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bool multi_monitor_in_sync;
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/* Controller Index of primary display - used in MCLK SMC switching hang
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* SW Workaround*/
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uint32_t crtc_index;
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/* htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/
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uint32_t line_time_in_us;
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bool invalid_vblank_time;
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uint32_t display_clk;
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/*
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* for given display configuration if multimonitormnsync == false then
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* Memory clock DPMS with this latency or below is allowed, DPMS with
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* higher latency not allowed.
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*/
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uint32_t dce_tolerable_mclk_in_active_latency;
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uint32_t min_dcef_set_clk;
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uint32_t min_dcef_deep_sleep_set_clk;
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};
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struct amd_pp_simple_clock_info {
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uint32_t engine_max_clock;
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uint32_t memory_max_clock;
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uint32_t level;
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};
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enum PP_DAL_POWERLEVEL {
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PP_DAL_POWERLEVEL_INVALID = 0,
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PP_DAL_POWERLEVEL_ULTRALOW,
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PP_DAL_POWERLEVEL_LOW,
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PP_DAL_POWERLEVEL_NOMINAL,
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PP_DAL_POWERLEVEL_PERFORMANCE,
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PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW,
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PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW,
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PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL,
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PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE,
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PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1,
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PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1,
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PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1,
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PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1,
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};
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struct amd_pp_clock_info {
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uint32_t min_engine_clock;
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uint32_t max_engine_clock;
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uint32_t min_memory_clock;
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uint32_t max_memory_clock;
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uint32_t min_bus_bandwidth;
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uint32_t max_bus_bandwidth;
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uint32_t max_engine_clock_in_sr;
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uint32_t min_engine_clock_in_sr;
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enum PP_DAL_POWERLEVEL max_clocks_state;
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};
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enum amd_pp_clock_type {
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amd_pp_disp_clock = 1,
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amd_pp_sys_clock,
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amd_pp_mem_clock,
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amd_pp_dcef_clock,
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amd_pp_soc_clock,
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amd_pp_pixel_clock,
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amd_pp_phy_clock,
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amd_pp_dcf_clock,
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amd_pp_dpp_clock,
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amd_pp_f_clock = amd_pp_dcef_clock,
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};
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#define MAX_NUM_CLOCKS 16
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struct amd_pp_clocks {
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uint32_t count;
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uint32_t clock[MAX_NUM_CLOCKS];
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uint32_t latency[MAX_NUM_CLOCKS];
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};
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struct pp_clock_with_latency {
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uint32_t clocks_in_khz;
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uint32_t latency_in_us;
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@ -45,6 +184,11 @@ struct pp_clock_levels_with_voltage {
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struct pp_clock_with_voltage data[PP_MAX_CLOCK_LEVELS];
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};
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struct pp_display_clock_request {
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enum amd_pp_clock_type clock_type;
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uint32_t clock_freq_in_khz;
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};
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#define PP_MAX_WM_SETS 4
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enum pp_wm_set_id {
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@ -64,144 +64,6 @@ struct amd_pp_init {
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uint32_t feature_mask;
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};
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enum amd_pp_display_config_type{
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AMD_PP_DisplayConfigType_None = 0,
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AMD_PP_DisplayConfigType_DP54 ,
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AMD_PP_DisplayConfigType_DP432 ,
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AMD_PP_DisplayConfigType_DP324 ,
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AMD_PP_DisplayConfigType_DP27,
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AMD_PP_DisplayConfigType_DP243,
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AMD_PP_DisplayConfigType_DP216,
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AMD_PP_DisplayConfigType_DP162,
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AMD_PP_DisplayConfigType_HDMI6G ,
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AMD_PP_DisplayConfigType_HDMI297 ,
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AMD_PP_DisplayConfigType_HDMI162,
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AMD_PP_DisplayConfigType_LVDS,
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AMD_PP_DisplayConfigType_DVI,
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AMD_PP_DisplayConfigType_WIRELESS,
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AMD_PP_DisplayConfigType_VGA
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};
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struct single_display_configuration
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{
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uint32_t controller_index;
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uint32_t controller_id;
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uint32_t signal_type;
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uint32_t display_state;
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/* phy id for the primary internal transmitter */
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uint8_t primary_transmitter_phyi_d;
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/* bitmap with the active lanes */
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uint8_t primary_transmitter_active_lanemap;
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/* phy id for the secondary internal transmitter (for dual-link dvi) */
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uint8_t secondary_transmitter_phy_id;
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/* bitmap with the active lanes */
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uint8_t secondary_transmitter_active_lanemap;
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/* misc phy settings for SMU. */
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uint32_t config_flags;
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uint32_t display_type;
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uint32_t view_resolution_cx;
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uint32_t view_resolution_cy;
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enum amd_pp_display_config_type displayconfigtype;
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uint32_t vertical_refresh; /* for active display */
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};
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#define MAX_NUM_DISPLAY 32
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struct amd_pp_display_configuration {
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bool nb_pstate_switch_disable;/* controls NB PState switch */
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bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
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bool cpu_pstate_disable;
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uint32_t cpu_pstate_separation_time;
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uint32_t num_display; /* total number of display*/
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uint32_t num_path_including_non_display;
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uint32_t crossfire_display_index;
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uint32_t min_mem_set_clock;
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uint32_t min_core_set_clock;
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/* unit 10KHz x bit*/
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uint32_t min_bus_bandwidth;
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/* minimum required stutter sclk, in 10khz uint32_t ulMinCoreSetClk;*/
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uint32_t min_core_set_clock_in_sr;
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struct single_display_configuration displays[MAX_NUM_DISPLAY];
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uint32_t vrefresh; /* for active display*/
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uint32_t min_vblank_time; /* for active display*/
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bool multi_monitor_in_sync;
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/* Controller Index of primary display - used in MCLK SMC switching hang
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* SW Workaround*/
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uint32_t crtc_index;
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/* htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/
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uint32_t line_time_in_us;
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bool invalid_vblank_time;
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uint32_t display_clk;
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/*
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* for given display configuration if multimonitormnsync == false then
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* Memory clock DPMS with this latency or below is allowed, DPMS with
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* higher latency not allowed.
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*/
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uint32_t dce_tolerable_mclk_in_active_latency;
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uint32_t min_dcef_set_clk;
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uint32_t min_dcef_deep_sleep_set_clk;
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};
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struct amd_pp_simple_clock_info {
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uint32_t engine_max_clock;
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uint32_t memory_max_clock;
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uint32_t level;
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};
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enum PP_DAL_POWERLEVEL {
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PP_DAL_POWERLEVEL_INVALID = 0,
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PP_DAL_POWERLEVEL_ULTRALOW,
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PP_DAL_POWERLEVEL_LOW,
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PP_DAL_POWERLEVEL_NOMINAL,
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PP_DAL_POWERLEVEL_PERFORMANCE,
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PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW,
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PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW,
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PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL,
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PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE,
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PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1,
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PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1,
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PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1,
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PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1,
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};
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struct amd_pp_clock_info {
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uint32_t min_engine_clock;
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uint32_t max_engine_clock;
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uint32_t min_memory_clock;
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uint32_t max_memory_clock;
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uint32_t min_bus_bandwidth;
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uint32_t max_bus_bandwidth;
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uint32_t max_engine_clock_in_sr;
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uint32_t min_engine_clock_in_sr;
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enum PP_DAL_POWERLEVEL max_clocks_state;
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};
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enum amd_pp_clock_type {
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amd_pp_disp_clock = 1,
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amd_pp_sys_clock,
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amd_pp_mem_clock,
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amd_pp_dcef_clock,
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amd_pp_soc_clock,
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amd_pp_pixel_clock,
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amd_pp_phy_clock,
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amd_pp_dcf_clock,
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amd_pp_dpp_clock,
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amd_pp_f_clock = amd_pp_dcef_clock,
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};
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#define MAX_NUM_CLOCKS 16
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struct amd_pp_clocks {
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uint32_t count;
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uint32_t clock[MAX_NUM_CLOCKS];
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uint32_t latency[MAX_NUM_CLOCKS];
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};
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enum {
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@ -223,11 +85,6 @@ struct pp_gpu_power {
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uint32_t average_gpu_power;
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};
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struct pp_display_clock_request {
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enum amd_pp_clock_type clock_type;
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uint32_t clock_freq_in_khz;
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};
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#define PP_GROUP_MASK 0xF0000000
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#define PP_GROUP_SHIFT 28
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