forked from Minki/linux
mmc: sdhci: fix minimum clock rate for v3 controller
For SDHCIv3+ with programmable clock mode, minimal clock frequency is still base clock / max(divider). Minimal programmable clock frequency is always greater than minimal divided clock frequency. Without this patch, SDHCI uses out-of-spec initial frequency when multiplier is big enough: mmc1: mmc_rescan_try_freq: trying to init card at 468750 Hz [for 480 MHz source clock divided by 1024] The code in sdhci_calc_clk() already chooses a correct SDCLK clock mode. Fixes:c3ed387762
("mmc: sdhci: add support for programmable clock mode") Cc: <stable@vger.kernel.org> #4f6aa3264a
: mmc: tegra: Only advertise UHS modes if IO regulator is present Cc: <stable@vger.kernel.org> Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/ffb489519a446caffe7a0a05c4b9372bd52397bb.1579082031.git.mirq-linux@rere.qmqm.pl Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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@ -3913,11 +3913,13 @@ int sdhci_setup_host(struct sdhci_host *host)
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if (host->ops->get_min_clock)
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mmc->f_min = host->ops->get_min_clock(host);
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else if (host->version >= SDHCI_SPEC_300) {
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if (host->clk_mul) {
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mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
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if (host->clk_mul)
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max_clk = host->max_clk * host->clk_mul;
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} else
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mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
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/*
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* Divided Clock Mode minimum clock rate is always less than
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* Programmable Clock Mode minimum clock rate.
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*/
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mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
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} else
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mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
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