net: broadcom: share header defining UniMAC registers
UniMAC is integrated into multiple Broadcom's Ethernet controllers so use a shared header file for it and avoid some code duplication. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Acked-by: Doug Berger <opendmb@gmail.com> Link: https://lore.kernel.org/r/20210107180051.1542-2-zajec5@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Rafał Miłecki
Jakub Kicinski
parent
12cf8e7572
commit
28e303da55
@ -3626,6 +3626,7 @@ S: Supported
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F: Documentation/devicetree/bindings/net/brcm,bcmgenet.txt
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F: Documentation/devicetree/bindings/net/brcm,unimac-mdio.txt
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F: drivers/net/ethernet/broadcom/genet/
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F: drivers/net/ethernet/broadcom/unimac.h
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F: drivers/net/mdio/mdio-bcm-unimac.c
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F: include/linux/platform_data/bcmgenet.h
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F: include/linux/platform_data/mdio-bcm-unimac.h
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@ -3738,6 +3739,7 @@ L: bcm-kernel-feedback-list@broadcom.com
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L: netdev@vger.kernel.org
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S: Supported
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F: drivers/net/ethernet/broadcom/bcmsysport.*
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F: drivers/net/ethernet/broadcom/unimac.h
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BROADCOM TG3 GIGABIT ETHERNET DRIVER
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M: Siva Reddy Kallam <siva.kallam@broadcom.com>
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@ -13,6 +13,8 @@
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#include <linux/if_vlan.h>
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#include <linux/dim.h>
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#include "unimac.h"
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/* Receive/transmit descriptor format */
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#define DESC_ADDR_HI_STATUS_LEN 0x00
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#define DESC_ADDR_HI_SHIFT 0
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@ -213,39 +215,6 @@ struct bcm_rsb {
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/* UniMAC offset and defines */
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#define SYS_PORT_UMAC_OFFSET 0x800
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#define UMAC_CMD 0x008
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#define CMD_TX_EN (1 << 0)
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#define CMD_RX_EN (1 << 1)
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#define CMD_SPEED_SHIFT 2
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#define CMD_SPEED_10 0
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#define CMD_SPEED_100 1
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#define CMD_SPEED_1000 2
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#define CMD_SPEED_2500 3
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#define CMD_SPEED_MASK 3
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#define CMD_PROMISC (1 << 4)
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#define CMD_PAD_EN (1 << 5)
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#define CMD_CRC_FWD (1 << 6)
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#define CMD_PAUSE_FWD (1 << 7)
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#define CMD_RX_PAUSE_IGNORE (1 << 8)
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#define CMD_TX_ADDR_INS (1 << 9)
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#define CMD_HD_EN (1 << 10)
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#define CMD_SW_RESET (1 << 13)
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#define CMD_LCL_LOOP_EN (1 << 15)
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#define CMD_AUTO_CONFIG (1 << 22)
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#define CMD_CNTL_FRM_EN (1 << 23)
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#define CMD_NO_LEN_CHK (1 << 24)
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#define CMD_RMT_LOOP_EN (1 << 25)
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#define CMD_PRBL_EN (1 << 27)
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#define CMD_TX_PAUSE_IGNORE (1 << 28)
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#define CMD_TX_RX_EN (1 << 29)
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#define CMD_RUNT_FILTER_DIS (1 << 30)
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#define UMAC_MAC0 0x00c
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#define UMAC_MAC1 0x010
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#define UMAC_MAX_FRAME_LEN 0x014
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#define UMAC_TX_FLUSH 0x334
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#define UMAC_MIB_START 0x400
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/* There is a 0xC gap between the end of RX and beginning of TX stats and then
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@ -749,22 +749,22 @@ error:
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static void bgmac_umac_cmd_maskset(struct bgmac *bgmac, u32 mask, u32 set,
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bool force)
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{
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u32 cmdcfg = bgmac_umac_read(bgmac, BGMAC_CMDCFG);
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u32 cmdcfg = bgmac_umac_read(bgmac, UMAC_CMD);
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u32 new_val = (cmdcfg & mask) | set;
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u32 cmdcfg_sr;
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if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4)
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cmdcfg_sr = BGMAC_CMDCFG_SR_REV4;
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cmdcfg_sr = CMD_SW_RESET;
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else
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cmdcfg_sr = BGMAC_CMDCFG_SR_REV0;
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cmdcfg_sr = CMD_SW_RESET_OLD;
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bgmac_umac_maskset(bgmac, BGMAC_CMDCFG, ~0, cmdcfg_sr);
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bgmac_umac_maskset(bgmac, UMAC_CMD, ~0, cmdcfg_sr);
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udelay(2);
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if (new_val != cmdcfg || force)
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bgmac_umac_write(bgmac, BGMAC_CMDCFG, new_val);
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bgmac_umac_write(bgmac, UMAC_CMD, new_val);
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bgmac_umac_maskset(bgmac, BGMAC_CMDCFG, ~cmdcfg_sr, 0);
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bgmac_umac_maskset(bgmac, UMAC_CMD, ~cmdcfg_sr, 0);
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udelay(2);
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}
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@ -773,9 +773,9 @@ static void bgmac_write_mac_address(struct bgmac *bgmac, u8 *addr)
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u32 tmp;
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tmp = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
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bgmac_umac_write(bgmac, BGMAC_MACADDR_HIGH, tmp);
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bgmac_umac_write(bgmac, UMAC_MAC0, tmp);
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tmp = (addr[4] << 8) | addr[5];
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bgmac_umac_write(bgmac, BGMAC_MACADDR_LOW, tmp);
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bgmac_umac_write(bgmac, UMAC_MAC1, tmp);
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}
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static void bgmac_set_rx_mode(struct net_device *net_dev)
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@ -783,9 +783,9 @@ static void bgmac_set_rx_mode(struct net_device *net_dev)
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struct bgmac *bgmac = netdev_priv(net_dev);
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if (net_dev->flags & IFF_PROMISC)
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bgmac_umac_cmd_maskset(bgmac, ~0, BGMAC_CMDCFG_PROM, true);
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bgmac_umac_cmd_maskset(bgmac, ~0, CMD_PROMISC, true);
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else
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bgmac_umac_cmd_maskset(bgmac, ~BGMAC_CMDCFG_PROM, 0, true);
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bgmac_umac_cmd_maskset(bgmac, ~CMD_PROMISC, 0, true);
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}
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#if 0 /* We don't use that regs yet */
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@ -825,21 +825,21 @@ static void bgmac_clear_mib(struct bgmac *bgmac)
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/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */
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static void bgmac_mac_speed(struct bgmac *bgmac)
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{
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u32 mask = ~(BGMAC_CMDCFG_ES_MASK | BGMAC_CMDCFG_HD);
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u32 mask = ~(CMD_SPEED_MASK << CMD_SPEED_SHIFT | CMD_HD_EN);
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u32 set = 0;
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switch (bgmac->mac_speed) {
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case SPEED_10:
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set |= BGMAC_CMDCFG_ES_10;
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set |= CMD_SPEED_10 << CMD_SPEED_SHIFT;
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break;
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case SPEED_100:
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set |= BGMAC_CMDCFG_ES_100;
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set |= CMD_SPEED_100 << CMD_SPEED_SHIFT;
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break;
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case SPEED_1000:
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set |= BGMAC_CMDCFG_ES_1000;
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set |= CMD_SPEED_1000 << CMD_SPEED_SHIFT;
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break;
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case SPEED_2500:
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set |= BGMAC_CMDCFG_ES_2500;
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set |= CMD_SPEED_2500 << CMD_SPEED_SHIFT;
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break;
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default:
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dev_err(bgmac->dev, "Unsupported speed: %d\n",
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@ -847,7 +847,7 @@ static void bgmac_mac_speed(struct bgmac *bgmac)
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}
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if (bgmac->mac_duplex == DUPLEX_HALF)
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set |= BGMAC_CMDCFG_HD;
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set |= CMD_HD_EN;
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bgmac_umac_cmd_maskset(bgmac, mask, set, true);
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}
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@ -917,7 +917,7 @@ static void bgmac_chip_reset(struct bgmac *bgmac)
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for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
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bgmac_dma_tx_reset(bgmac, &bgmac->tx_ring[i]);
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bgmac_umac_cmd_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
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bgmac_umac_cmd_maskset(bgmac, ~0, CMD_LCL_LOOP_EN, false);
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udelay(1);
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for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
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@ -986,32 +986,32 @@ static void bgmac_chip_reset(struct bgmac *bgmac)
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}
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/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_reset
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* Specs don't say about using BGMAC_CMDCFG_SR, but in this routine
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* BGMAC_CMDCFG is read _after_ putting chip in a reset. So it has to
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* Specs don't say about using UMAC_CMD_SR, but in this routine
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* UMAC_CMD is read _after_ putting chip in a reset. So it has to
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* be keps until taking MAC out of the reset.
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*/
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if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4)
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cmdcfg_sr = BGMAC_CMDCFG_SR_REV4;
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cmdcfg_sr = CMD_SW_RESET;
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else
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cmdcfg_sr = BGMAC_CMDCFG_SR_REV0;
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cmdcfg_sr = CMD_SW_RESET_OLD;
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bgmac_umac_cmd_maskset(bgmac,
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~(BGMAC_CMDCFG_TE |
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BGMAC_CMDCFG_RE |
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BGMAC_CMDCFG_RPI |
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BGMAC_CMDCFG_TAI |
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BGMAC_CMDCFG_HD |
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BGMAC_CMDCFG_ML |
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BGMAC_CMDCFG_CFE |
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BGMAC_CMDCFG_RL |
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BGMAC_CMDCFG_RED |
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BGMAC_CMDCFG_PE |
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BGMAC_CMDCFG_TPI |
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BGMAC_CMDCFG_PAD_EN |
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BGMAC_CMDCFG_PF),
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BGMAC_CMDCFG_PROM |
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BGMAC_CMDCFG_NLC |
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BGMAC_CMDCFG_CFE |
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~(CMD_TX_EN |
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CMD_RX_EN |
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CMD_RX_PAUSE_IGNORE |
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CMD_TX_ADDR_INS |
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CMD_HD_EN |
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CMD_LCL_LOOP_EN |
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CMD_CNTL_FRM_EN |
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CMD_RMT_LOOP_EN |
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CMD_RX_ERR_DISC |
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CMD_PRBL_EN |
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CMD_TX_PAUSE_IGNORE |
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CMD_PAD_EN |
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CMD_PAUSE_FWD),
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CMD_PROMISC |
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CMD_NO_LEN_CHK |
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CMD_CNTL_FRM_EN |
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cmdcfg_sr,
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false);
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bgmac->mac_speed = SPEED_UNKNOWN;
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@ -1049,16 +1049,16 @@ static void bgmac_enable(struct bgmac *bgmac)
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u32 mode;
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if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4)
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cmdcfg_sr = BGMAC_CMDCFG_SR_REV4;
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cmdcfg_sr = CMD_SW_RESET;
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else
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cmdcfg_sr = BGMAC_CMDCFG_SR_REV0;
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cmdcfg_sr = CMD_SW_RESET_OLD;
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cmdcfg = bgmac_umac_read(bgmac, BGMAC_CMDCFG);
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bgmac_umac_cmd_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE),
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cmdcfg = bgmac_umac_read(bgmac, UMAC_CMD);
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bgmac_umac_cmd_maskset(bgmac, ~(CMD_TX_EN | CMD_RX_EN),
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cmdcfg_sr, true);
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udelay(2);
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cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE;
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bgmac_umac_write(bgmac, BGMAC_CMDCFG, cmdcfg);
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cmdcfg |= CMD_TX_EN | CMD_RX_EN;
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bgmac_umac_write(bgmac, UMAC_CMD, cmdcfg);
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mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
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BGMAC_DS_MM_SHIFT;
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@ -1078,7 +1078,7 @@ static void bgmac_enable(struct bgmac *bgmac)
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fl_ctl = 0x03cb04cb;
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bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl);
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bgmac_umac_write(bgmac, BGMAC_PAUSE_CTL, 0x27fff);
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bgmac_umac_write(bgmac, UMAC_PAUSE_CTRL, 0x27fff);
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}
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if (bgmac->feature_flags & BGMAC_FEAT_SET_RXQ_CLK) {
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@ -1105,18 +1105,18 @@ static void bgmac_chip_init(struct bgmac *bgmac)
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bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT);
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/* Enable 802.3x tx flow control (honor received PAUSE frames) */
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bgmac_umac_cmd_maskset(bgmac, ~BGMAC_CMDCFG_RPI, 0, true);
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bgmac_umac_cmd_maskset(bgmac, ~CMD_RX_PAUSE_IGNORE, 0, true);
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bgmac_set_rx_mode(bgmac->net_dev);
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bgmac_write_mac_address(bgmac, bgmac->net_dev->dev_addr);
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if (bgmac->loopback)
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bgmac_umac_cmd_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
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bgmac_umac_cmd_maskset(bgmac, ~0, CMD_LCL_LOOP_EN, false);
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else
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bgmac_umac_cmd_maskset(bgmac, ~BGMAC_CMDCFG_ML, 0, false);
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bgmac_umac_cmd_maskset(bgmac, ~CMD_LCL_LOOP_EN, 0, false);
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bgmac_umac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN);
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bgmac_umac_write(bgmac, UMAC_MAX_FRAME_LEN, 32 + ETHER_MAX_LEN);
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bgmac_chip_intrs_on(bgmac);
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@ -1252,7 +1252,7 @@ static int bgmac_change_mtu(struct net_device *net_dev, int mtu)
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{
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struct bgmac *bgmac = netdev_priv(net_dev);
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bgmac_umac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + mtu);
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bgmac_umac_write(bgmac, UMAC_MAX_FRAME_LEN, 32 + mtu);
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return 0;
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}
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@ -4,6 +4,8 @@
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#include <linux/netdevice.h>
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#include "unimac.h"
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#define BGMAC_DEV_CTL 0x000
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#define BGMAC_DC_TSM 0x00000002
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#define BGMAC_DC_CFCO 0x00000004
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@ -169,47 +171,7 @@
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#define BGMAC_RX_NONPAUSE_PKTS 0x420
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#define BGMAC_RX_SACHANGES 0x424
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#define BGMAC_RX_UNI_PKTS 0x428
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#define BGMAC_UNIMAC_VERSION 0x800
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#define BGMAC_HDBKP_CTL 0x804
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#define BGMAC_CMDCFG 0x808 /* Configuration */
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#define BGMAC_CMDCFG_TE 0x00000001 /* Set to activate TX */
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#define BGMAC_CMDCFG_RE 0x00000002 /* Set to activate RX */
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#define BGMAC_CMDCFG_ES_MASK 0x0000000c /* Ethernet speed see gmac_speed */
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#define BGMAC_CMDCFG_ES_10 0x00000000
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#define BGMAC_CMDCFG_ES_100 0x00000004
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#define BGMAC_CMDCFG_ES_1000 0x00000008
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#define BGMAC_CMDCFG_ES_2500 0x0000000C
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#define BGMAC_CMDCFG_PROM 0x00000010 /* Set to activate promiscuous mode */
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#define BGMAC_CMDCFG_PAD_EN 0x00000020
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#define BGMAC_CMDCFG_CF 0x00000040
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#define BGMAC_CMDCFG_PF 0x00000080
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#define BGMAC_CMDCFG_RPI 0x00000100 /* Unset to enable 802.3x tx flow control */
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#define BGMAC_CMDCFG_TAI 0x00000200
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#define BGMAC_CMDCFG_HD 0x00000400 /* Set if in half duplex mode */
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#define BGMAC_CMDCFG_HD_SHIFT 10
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#define BGMAC_CMDCFG_SR_REV0 0x00000800 /* Set to reset mode, for core rev 0-3 */
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#define BGMAC_CMDCFG_SR_REV4 0x00002000 /* Set to reset mode, for core rev >= 4 */
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#define BGMAC_CMDCFG_ML 0x00008000 /* Set to activate mac loopback mode */
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#define BGMAC_CMDCFG_AE 0x00400000
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#define BGMAC_CMDCFG_CFE 0x00800000
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#define BGMAC_CMDCFG_NLC 0x01000000
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#define BGMAC_CMDCFG_RL 0x02000000
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#define BGMAC_CMDCFG_RED 0x04000000
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#define BGMAC_CMDCFG_PE 0x08000000
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#define BGMAC_CMDCFG_TPI 0x10000000
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#define BGMAC_CMDCFG_AT 0x20000000
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#define BGMAC_MACADDR_HIGH 0x80c /* High 4 octets of own mac address */
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#define BGMAC_MACADDR_LOW 0x810 /* Low 2 octets of own mac address */
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#define BGMAC_RXMAX_LENGTH 0x814 /* Max receive frame length with vlan tag */
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#define BGMAC_PAUSEQUANTA 0x818
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#define BGMAC_MAC_MODE 0x844
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#define BGMAC_OUTERTAG 0x848
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#define BGMAC_INNERTAG 0x84c
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#define BGMAC_TXIPG 0x85c
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#define BGMAC_PAUSE_CTL 0xb30
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#define BGMAC_TX_FLUSH 0xb34
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#define BGMAC_RX_STATUS 0xb38
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#define BGMAC_TX_STATUS 0xb3c
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#define BGMAC_UNIMAC 0x800
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/* BCMA GMAC core specific IO Control (BCMA_IOCTL) flags */
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#define BGMAC_BCMA_IOCTL_SW_CLKEN 0x00000004 /* PHY Clock Enable */
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@ -558,12 +520,12 @@ static inline void bgmac_write(struct bgmac *bgmac, u16 offset, u32 value)
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static inline u32 bgmac_umac_read(struct bgmac *bgmac, u16 offset)
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{
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return bgmac_read(bgmac, offset);
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return bgmac_read(bgmac, BGMAC_UNIMAC + offset);
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}
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static inline void bgmac_umac_write(struct bgmac *bgmac, u16 offset, u32 value)
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{
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bgmac_write(bgmac, offset, value);
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bgmac_write(bgmac, BGMAC_UNIMAC + offset, value);
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}
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static inline u32 bgmac_idm_read(struct bgmac *bgmac, u16 offset)
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@ -621,7 +583,7 @@ static inline void bgmac_set(struct bgmac *bgmac, u16 offset, u32 set)
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static inline void bgmac_umac_maskset(struct bgmac *bgmac, u16 offset, u32 mask, u32 set)
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{
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bgmac_maskset(bgmac, offset, mask, set);
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bgmac_maskset(bgmac, BGMAC_UNIMAC + offset, mask, set);
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}
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static inline int bgmac_phy_connect(struct bgmac *bgmac)
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@ -16,6 +16,8 @@
|
||||
#include <linux/dim.h>
|
||||
#include <linux/ethtool.h>
|
||||
|
||||
#include "../unimac.h"
|
||||
|
||||
/* total number of Buffer Descriptors, same for Rx/Tx */
|
||||
#define TOTAL_DESC 256
|
||||
|
||||
@ -150,63 +152,6 @@ struct bcmgenet_mib_counters {
|
||||
u32 tx_realloc_tsb_failed;
|
||||
};
|
||||
|
||||
#define UMAC_HD_BKP_CTRL 0x004
|
||||
#define HD_FC_EN (1 << 0)
|
||||
#define HD_FC_BKOFF_OK (1 << 1)
|
||||
#define IPG_CONFIG_RX_SHIFT 2
|
||||
#define IPG_CONFIG_RX_MASK 0x1F
|
||||
|
||||
#define UMAC_CMD 0x008
|
||||
#define CMD_TX_EN (1 << 0)
|
||||
#define CMD_RX_EN (1 << 1)
|
||||
#define UMAC_SPEED_10 0
|
||||
#define UMAC_SPEED_100 1
|
||||
#define UMAC_SPEED_1000 2
|
||||
#define UMAC_SPEED_2500 3
|
||||
#define CMD_SPEED_SHIFT 2
|
||||
#define CMD_SPEED_MASK 3
|
||||
#define CMD_PROMISC (1 << 4)
|
||||
#define CMD_PAD_EN (1 << 5)
|
||||
#define CMD_CRC_FWD (1 << 6)
|
||||
#define CMD_PAUSE_FWD (1 << 7)
|
||||
#define CMD_RX_PAUSE_IGNORE (1 << 8)
|
||||
#define CMD_TX_ADDR_INS (1 << 9)
|
||||
#define CMD_HD_EN (1 << 10)
|
||||
#define CMD_SW_RESET (1 << 13)
|
||||
#define CMD_LCL_LOOP_EN (1 << 15)
|
||||
#define CMD_AUTO_CONFIG (1 << 22)
|
||||
#define CMD_CNTL_FRM_EN (1 << 23)
|
||||
#define CMD_NO_LEN_CHK (1 << 24)
|
||||
#define CMD_RMT_LOOP_EN (1 << 25)
|
||||
#define CMD_PRBL_EN (1 << 27)
|
||||
#define CMD_TX_PAUSE_IGNORE (1 << 28)
|
||||
#define CMD_TX_RX_EN (1 << 29)
|
||||
#define CMD_RUNT_FILTER_DIS (1 << 30)
|
||||
|
||||
#define UMAC_MAC0 0x00C
|
||||
#define UMAC_MAC1 0x010
|
||||
#define UMAC_MAX_FRAME_LEN 0x014
|
||||
|
||||
#define UMAC_MODE 0x44
|
||||
#define MODE_LINK_STATUS (1 << 5)
|
||||
|
||||
#define UMAC_EEE_CTRL 0x064
|
||||
#define EN_LPI_RX_PAUSE (1 << 0)
|
||||
#define EN_LPI_TX_PFC (1 << 1)
|
||||
#define EN_LPI_TX_PAUSE (1 << 2)
|
||||
#define EEE_EN (1 << 3)
|
||||
#define RX_FIFO_CHECK (1 << 4)
|
||||
#define EEE_TX_CLK_DIS (1 << 5)
|
||||
#define DIS_EEE_10M (1 << 6)
|
||||
#define LP_IDLE_PREDICTION_MODE (1 << 7)
|
||||
|
||||
#define UMAC_EEE_LPI_TIMER 0x068
|
||||
#define UMAC_EEE_WAKE_TIMER 0x06C
|
||||
#define UMAC_EEE_REF_COUNT 0x070
|
||||
#define EEE_REFERENCE_COUNT_MASK 0xffff
|
||||
|
||||
#define UMAC_TX_FLUSH 0x334
|
||||
|
||||
#define UMAC_MIB_START 0x400
|
||||
|
||||
#define UMAC_MDIO_CMD 0x614
|
||||
|
||||
@ -63,11 +63,11 @@ void bcmgenet_mii_setup(struct net_device *dev)
|
||||
|
||||
/* speed */
|
||||
if (phydev->speed == SPEED_1000)
|
||||
cmd_bits = UMAC_SPEED_1000;
|
||||
cmd_bits = CMD_SPEED_1000;
|
||||
else if (phydev->speed == SPEED_100)
|
||||
cmd_bits = UMAC_SPEED_100;
|
||||
cmd_bits = CMD_SPEED_100;
|
||||
else
|
||||
cmd_bits = UMAC_SPEED_10;
|
||||
cmd_bits = CMD_SPEED_10;
|
||||
cmd_bits <<= CMD_SPEED_SHIFT;
|
||||
|
||||
/* duplex */
|
||||
|
||||
68
drivers/net/ethernet/broadcom/unimac.h
Normal file
68
drivers/net/ethernet/broadcom/unimac.h
Normal file
@ -0,0 +1,68 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
#ifndef __UNIMAC_H
|
||||
#define __UNIMAC_H
|
||||
|
||||
#define UMAC_HD_BKP_CTRL 0x004
|
||||
#define HD_FC_EN (1 << 0)
|
||||
#define HD_FC_BKOFF_OK (1 << 1)
|
||||
#define IPG_CONFIG_RX_SHIFT 2
|
||||
#define IPG_CONFIG_RX_MASK 0x1F
|
||||
#define UMAC_CMD 0x008
|
||||
#define CMD_TX_EN (1 << 0)
|
||||
#define CMD_RX_EN (1 << 1)
|
||||
#define CMD_SPEED_10 0
|
||||
#define CMD_SPEED_100 1
|
||||
#define CMD_SPEED_1000 2
|
||||
#define CMD_SPEED_2500 3
|
||||
#define CMD_SPEED_SHIFT 2
|
||||
#define CMD_SPEED_MASK 3
|
||||
#define CMD_PROMISC (1 << 4)
|
||||
#define CMD_PAD_EN (1 << 5)
|
||||
#define CMD_CRC_FWD (1 << 6)
|
||||
#define CMD_PAUSE_FWD (1 << 7)
|
||||
#define CMD_RX_PAUSE_IGNORE (1 << 8)
|
||||
#define CMD_TX_ADDR_INS (1 << 9)
|
||||
#define CMD_HD_EN (1 << 10)
|
||||
#define CMD_SW_RESET_OLD (1 << 11)
|
||||
#define CMD_SW_RESET (1 << 13)
|
||||
#define CMD_LCL_LOOP_EN (1 << 15)
|
||||
#define CMD_AUTO_CONFIG (1 << 22)
|
||||
#define CMD_CNTL_FRM_EN (1 << 23)
|
||||
#define CMD_NO_LEN_CHK (1 << 24)
|
||||
#define CMD_RMT_LOOP_EN (1 << 25)
|
||||
#define CMD_RX_ERR_DISC (1 << 26)
|
||||
#define CMD_PRBL_EN (1 << 27)
|
||||
#define CMD_TX_PAUSE_IGNORE (1 << 28)
|
||||
#define CMD_TX_RX_EN (1 << 29)
|
||||
#define CMD_RUNT_FILTER_DIS (1 << 30)
|
||||
#define UMAC_MAC0 0x00c
|
||||
#define UMAC_MAC1 0x010
|
||||
#define UMAC_MAX_FRAME_LEN 0x014
|
||||
#define UMAC_PAUSE_QUANTA 0x018
|
||||
#define UMAC_MODE 0x044
|
||||
#define MODE_LINK_STATUS (1 << 5)
|
||||
#define UMAC_FRM_TAG0 0x048 /* outer tag */
|
||||
#define UMAC_FRM_TAG1 0x04c /* inner tag */
|
||||
#define UMAC_TX_IPG_LEN 0x05c
|
||||
#define UMAC_EEE_CTRL 0x064
|
||||
#define EN_LPI_RX_PAUSE (1 << 0)
|
||||
#define EN_LPI_TX_PFC (1 << 1)
|
||||
#define EN_LPI_TX_PAUSE (1 << 2)
|
||||
#define EEE_EN (1 << 3)
|
||||
#define RX_FIFO_CHECK (1 << 4)
|
||||
#define EEE_TX_CLK_DIS (1 << 5)
|
||||
#define DIS_EEE_10M (1 << 6)
|
||||
#define LP_IDLE_PREDICTION_MODE (1 << 7)
|
||||
#define UMAC_EEE_LPI_TIMER 0x068
|
||||
#define UMAC_EEE_WAKE_TIMER 0x06C
|
||||
#define UMAC_EEE_REF_COUNT 0x070
|
||||
#define EEE_REFERENCE_COUNT_MASK 0xffff
|
||||
#define UMAC_RX_IPG_INV 0x078
|
||||
#define UMAC_MACSEC_PROG_TX_CRC 0x310
|
||||
#define UMAC_MACSEC_CTRL 0x314
|
||||
#define UMAC_PAUSE_CTRL 0x330
|
||||
#define UMAC_TX_FLUSH 0x334
|
||||
#define UMAC_RX_FIFO_STATUS 0x338
|
||||
#define UMAC_TX_FIFO_STATUS 0x33c
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user