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mmc: sdhci-esdhc-imx: separate 100/200 MHz pinctrl states check

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As indicated by function esdhc_change_pinstate(), SDR50 and DDR50
require pins_100mhz, while SDR104 and HS400 require pins_200mhz.  Some
system design may support SDR50 and DDR50 with 100mhz pin state only
(without 200mhz one).  Currently the combined 100/200 MHz pinctrl state
check prevents such system from running SDR50 and DDR50.  Separate the
check to support such system design.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
Link: https://lore.kernel.org/r/20210326110214.28416-1-shawnguo@kernel.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Shawn Guo 2021-03-26 19:02:14 +08:00 committed by Ulf Hansson
parent f0bdf98fab
commit 25e8b9eb09
1 changed files with 4 additions and 4 deletions
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8
drivers/mmc/host/sdhci-esdhc-imx.c
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@ -434,10 +434,10 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
* Do not advertise faster UHS modes if there are no
* pinctrl states for 100MHz/200MHz.
*/
if (IS_ERR_OR_NULL(imx_data->pins_100mhz) ||
IS_ERR_OR_NULL(imx_data->pins_200mhz))
val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50
| SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
if (IS_ERR_OR_NULL(imx_data->pins_100mhz))
val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);
if (IS_ERR_OR_NULL(imx_data->pins_200mhz))
val &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
}
}