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ARC: [hsdk] Make it easier to add PAE40 region to DTB

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1. Bump top level address-cells/size-cells nodes to 2 (to ensure all
   down stream addresses are 64-bits, unless explicitly specified
   otherwise (in "soc" bus with all peripherals)

2. "memory" also specified with address/size 2

3. Add a commented reference for PAE40 region beyond 4GB physical
   address space

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
Vineet Gupta 2019-04-02 12:10:44 -07:00
parent 99bd5fcc50
commit 21cee1bd15
1 changed files with 7 additions and 6 deletions
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13
arch/arc/boot/dts/hsdk.dts
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@ -18,8 +18,8 @@
model = "snps,hsdk";
compatible = "snps,hsdk";
#address-cells = <1>;
#size-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
chosen {
bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
@ -105,7 +105,7 @@
#size-cells = <1>;
interrupt-parent = <&idu_intc>;
ranges = <0x00000000 0xf0000000 0x10000000>;
ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
cgu_rst: reset-controller@8a0 {
compatible = "snps,hsdk-reset";
@ -269,9 +269,10 @@
};
memory@80000000 {
#address-cells = <1>;
#size-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
device_type = "memory";
reg = <0x80000000 0x40000000>; /* 1 GiB */
reg = <0x0 0x80000000 0x0 0x40000000>; /* 1 GB lowmem */
/* 0x1 0x00000000 0x0 0x40000000>; 1 GB highmem */
};
};