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[media] media: i2c: tvp7002: rearrange description of structure members

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This patch rearranges the description of field members of
struct tvp7002_config. Also as the all the fields where accepting
a value either 0/1, made the members as bool.

Signed-off-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Lad, Prabhakar 2013-05-14 06:45:31 -03:00 committed by Mauro Carvalho Chehab
parent abc0fd734e
commit 19ec930574
1 changed files with 20 additions and 24 deletions
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44
include/media/tvp7002.h
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@ -28,31 +28,27 @@
#define TVP7002_MODULE_NAME "tvp7002"
/* Platform-dependent data
*
* clk_polarity:
* 0 -> data clocked out on rising edge of DATACLK signal
* 1 -> data clocked out on falling edge of DATACLK signal
* hs_polarity:
* 0 -> active low HSYNC output
* 1 -> active high HSYNC output
* sog_polarity:
* 0 -> normal operation
* 1 -> operation with polarity inverted
* vs_polarity:
* 0 -> active low VSYNC output
* 1 -> active high VSYNC output
* fid_polarity:
* 0 -> the field ID output is set to logic 1 for an odd
* field (field 1) and set to logic 0 for an even
* field (field 0).
* 1 -> operation with polarity inverted.
/**
* struct tvp7002_config - Platform dependent data
*@clk_polarity: Clock polarity
* 0 - Data clocked out on rising edge of DATACLK signal
* 1 - Data clocked out on falling edge of DATACLK signal
*@hs_polarity: HSYNC polarity
* 0 - Active low HSYNC output, 1 - Active high HSYNC output
*@vs_polarity: VSYNC Polarity
* 0 - Active low VSYNC output, 1 - Active high VSYNC output
*@fid_polarity: Active-high Field ID polarity.
* 0 - The field ID output is set to logic 1 for an odd field
* (field 1) and set to logic 0 for an even field (field 0).
* 1 - Operation with polarity inverted.
*@sog_polarity: Active high Sync on Green output polarity.
* 0 - Normal operation, 1 - Operation with polarity inverted
*/
struct tvp7002_config {
u8 clk_polarity;
u8 hs_polarity;
u8 vs_polarity;
u8 fid_polarity;
u8 sog_polarity;
bool clk_polarity;
bool hs_polarity;
bool vs_polarity;
bool fid_polarity;
bool sog_polarity;
};
#endif