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MIPS: ATH79: Add irq chip ar7240-misc-intc

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The ar7240 misc irq chip use ack handler
instead of ack_mask handler. All new ath79 chips use
the ar7240 misc irq chip

Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Acked-by: Alban Bedel <albeu@free.fr>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-mips@linux-mips.org
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: devicetree@vger.kernel.org
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/11164/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Alexander Couzens 2015-09-19 06:26:20 +02:00 committed by Ralf Baechle
parent 84dedd71cf
commit 19446da415
2 changed files with 28 additions and 2 deletions
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20
Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt
View File

@ -4,8 +4,8 @@ The MISC interrupt controller is a secondary controller for lower priority
interrupt.
Required Properties:
- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc"
as fallback
- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc" or
"qca,<soctype>-cpu-intc", "qca,ar7240-misc-intc"
- reg: Base address and size of the controllers memory area
- interrupt-parent: phandle of the parent interrupt controller.
- interrupts: Interrupt specifier for the controllers interrupt.
@ -13,6 +13,9 @@ Required Properties:
- #interrupt-cells : Specifies the number of cells needed to encode interrupt
source, should be 1
Compatible fallback depends on the SoC. Use ar7100 for ar71xx and ar913x,
use ar7240 for all other SoCs.
Please refer to interrupts.txt in this directory for details of the common
Interrupt Controllers bindings used by client devices.
@ -28,3 +31,16 @@ Example:
interrupt-controller;
#interrupt-cells = <1>;
};
Another example:
interrupt-controller@18060010 {
compatible = "qca,ar9331-misc-intc", qca,ar7240-misc-intc";
reg = <0x18060010 0x4>;
interrupt-parent = <&cpuintc>;
interrupts = <6>;
interrupt-controller;
#interrupt-cells = <1>;
};

10
arch/mips/ath79/irq.c
View File

@ -304,6 +304,16 @@ static int __init ar7100_misc_intc_of_init(
IRQCHIP_DECLARE(ar7100_misc_intc, "qca,ar7100-misc-intc",
ar7100_misc_intc_of_init);
static int __init ar7240_misc_intc_of_init(
struct device_node *node, struct device_node *parent)
{
ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
return ath79_misc_intc_of_init(node, parent);
}
IRQCHIP_DECLARE(ar7240_misc_intc, "qca,ar7240-misc-intc",
ar7240_misc_intc_of_init);
static int __init ar79_cpu_intc_of_init(
struct device_node *node, struct device_node *parent)
{