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arm64: dts: hisilicon: adjust whitespace around '='

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Fix whitespace coding style: use single space instead of tabs or
multiple spaces around '=' sign in property assignment.  No functional
changes (same DTB).

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220526204453.832681-1-krzysztof.kozlowski@linaro.org
This commit is contained in:
Krzysztof Kozlowski
2022-05-26 22:44:53 +02:00
parent 8c1be9336e
commit 11357f103f
6 changed files with 23 additions and 23 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
View File

@@ -49,9 +49,9 @@
ramoops@32000000 {
compatible = "ramoops";
reg = <0x0 0x32000000 0x0 0x00100000>;
record-size = <0x00020000>;
console-size = <0x00020000>;
ftrace-size = <0x00020000>;
record-size = <0x00020000>;
console-size = <0x00020000>;
ftrace-size = <0x00020000>;
};
};
@@ -63,9 +63,9 @@
compatible = "syscon-reboot-mode";
offset = <0x0>;
mode-normal = <0x77665501>;
mode-bootloader = <0x77665500>;
mode-recovery = <0x77665502>;
mode-normal = <0x77665501>;
mode-bootloader = <0x77665500>;
mode-recovery = <0x77665502>;
};
};

8
arch/arm64/boot/dts/hisilicon/hi3660.dtsi
View File

@@ -479,7 +479,7 @@
reg = <0x0 0xfdf00000 0x0 0x1000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
dma-names = "rx", "tx";
dmas = <&dma0 2 &dma0 3>;
dmas = <&dma0 2 &dma0 3>;
clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>,
<&crg_ctrl HI3660_CLK_GATE_UART1>;
clock-names = "uartclk", "apb_pclk";
@@ -493,7 +493,7 @@
reg = <0x0 0xfdf03000 0x0 0x1000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
dma-names = "rx", "tx";
dmas = <&dma0 4 &dma0 5>;
dmas = <&dma0 4 &dma0 5>;
clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>,
<&crg_ctrl HI3660_PCLK>;
clock-names = "uartclk", "apb_pclk";
@@ -519,7 +519,7 @@
reg = <0x0 0xfdf01000 0x0 0x1000>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
dma-names = "rx", "tx";
dmas = <&dma0 6 &dma0 7>;
dmas = <&dma0 6 &dma0 7>;
clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>,
<&crg_ctrl HI3660_CLK_GATE_UART4>;
clock-names = "uartclk", "apb_pclk";
@@ -533,7 +533,7 @@
reg = <0x0 0xfdf05000 0x0 0x1000>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
dma-names = "rx", "tx";
dmas = <&dma0 8 &dma0 9>;
dmas = <&dma0 8 &dma0 9>;
clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>,
<&crg_ctrl HI3660_CLK_GATE_UART5>;
clock-names = "uartclk", "apb_pclk";

2
arch/arm64/boot/dts/hisilicon/hi3670.dtsi
View File

@@ -324,7 +324,7 @@
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 13 4 &pmx0 7 17 1>;
gpio-ranges = <&pmx0 0 13 4 &pmx0 7 17 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&crg_ctrl HI3670_PCLK_GPIO3>;

12
arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
View File

@@ -54,9 +54,9 @@
ramoops@21f00000 {
compatible = "ramoops";
reg = <0x0 0x21f00000 0x0 0x00100000>;
record-size = <0x00020000>;
console-size = <0x00020000>;
ftrace-size = <0x00020000>;
record-size = <0x00020000>;
console-size = <0x00020000>;
ftrace-size = <0x00020000>;
};
/* global autoconfigured region for contiguous allocations */
@@ -76,9 +76,9 @@
compatible = "syscon-reboot-mode";
offset = <0x0>;
mode-normal = <0x77665501>;
mode-bootloader = <0x77665500>;
mode-recovery = <0x77665502>;
mode-normal = <0x77665501>;
mode-bootloader = <0x77665500>;
mode-recovery = <0x77665502>;
};
};

6
arch/arm64/boot/dts/hisilicon/hip06.dtsi
View File

@@ -537,7 +537,7 @@
port@1 {
reg = <1>;
serdes-syscon= <&serdes_ctrl>;
serdes-syscon = <&serdes_ctrl>;
port-rst-offset = <1>;
port-mode-offset = <1>;
media-type = "fiber";
@@ -546,7 +546,7 @@
port@4 {
reg = <4>;
phy-handle = <&phy0>;
serdes-syscon= <&serdes_ctrl>;
serdes-syscon = <&serdes_ctrl>;
port-rst-offset = <4>;
port-mode-offset = <2>;
media-type = "copper";
@@ -555,7 +555,7 @@
port@5 {
reg = <5>;
phy-handle = <&phy1>;
serdes-syscon= <&serdes_ctrl>;
serdes-syscon = <&serdes_ctrl>;
port-rst-offset = <5>;
port-mode-offset = <3>;
media-type = "copper";

6
arch/arm64/boot/dts/hisilicon/hip07.dtsi
View File

@@ -1422,7 +1422,7 @@
port@1 {
reg = <1>;
serdes-syscon= <&serdes_ctrl>;
serdes-syscon = <&serdes_ctrl>;
cpld-syscon = <&dsa_cpld 0x4>;
port-rst-offset = <1>;
port-mode-offset = <1>;
@@ -1433,7 +1433,7 @@
port@4 {
reg = <4>;
phy-handle = <&phy0>;
serdes-syscon= <&serdes_ctrl>;
serdes-syscon = <&serdes_ctrl>;
port-rst-offset = <4>;
port-mode-offset = <2>;
mc-mac-mask = [ff f0 00 00 00 00];
@@ -1443,7 +1443,7 @@
port@5 {
reg = <5>;
phy-handle = <&phy1>;
serdes-syscon= <&serdes_ctrl>;
serdes-syscon = <&serdes_ctrl>;
port-rst-offset = <5>;
port-mode-offset = <3>;
mc-mac-mask = [ff f0 00 00 00 00];