rtc: add xilinx zynqmp rtc driver
Add support for RTC controller found on Xilinx Zynq Ultrascale+ MPSoC platform. Signed-off-by: Suneel Garapati <suneel.garapati@xilinx.com> Acked-by: Moritz Fischer <moritz.fischer@ettus.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
This commit is contained in:
Suneel Garapati
Alexandre Belloni
parent
12ece40d91
commit
11143c19eb
@ -1116,6 +1116,13 @@ config RTC_DRV_OPAL
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This driver can also be built as a module. If so, the module
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will be called rtc-opal.
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config RTC_DRV_ZYNQMP
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tristate "Xilinx Zynq Ultrascale+ MPSoC RTC"
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depends on OF
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help
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If you say yes here you get support for the RTC controller found on
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Xilinx Zynq Ultrascale+ MPSoC.
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comment "on-CPU RTC drivers"
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config RTC_DRV_DAVINCI
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@ -159,3 +159,4 @@ obj-$(CONFIG_RTC_DRV_WM831X) += rtc-wm831x.o
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obj-$(CONFIG_RTC_DRV_WM8350) += rtc-wm8350.o
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obj-$(CONFIG_RTC_DRV_X1205) += rtc-x1205.o
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obj-$(CONFIG_RTC_DRV_XGENE) += rtc-xgene.o
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obj-$(CONFIG_RTC_DRV_ZYNQMP) += rtc-zynqmp.o
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279
drivers/rtc/rtc-zynqmp.c
Normal file
279
drivers/rtc/rtc-zynqmp.c
Normal file
@ -0,0 +1,279 @@
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/*
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* Xilinx Zynq Ultrascale+ MPSoC Real Time Clock Driver
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*
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* Copyright (C) 2015 Xilinx, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/rtc.h>
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/* RTC Registers */
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#define RTC_SET_TM_WR 0x00
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#define RTC_SET_TM_RD 0x04
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#define RTC_CALIB_WR 0x08
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#define RTC_CALIB_RD 0x0C
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#define RTC_CUR_TM 0x10
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#define RTC_CUR_TICK 0x14
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#define RTC_ALRM 0x18
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#define RTC_INT_STS 0x20
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#define RTC_INT_MASK 0x24
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#define RTC_INT_EN 0x28
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#define RTC_INT_DIS 0x2C
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#define RTC_CTRL 0x40
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#define RTC_FR_EN BIT(20)
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#define RTC_FR_DATSHIFT 16
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#define RTC_TICK_MASK 0xFFFF
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#define RTC_INT_SEC BIT(0)
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#define RTC_INT_ALRM BIT(1)
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#define RTC_OSC_EN BIT(24)
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#define RTC_CALIB_DEF 0x198233
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#define RTC_CALIB_MASK 0x1FFFFF
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#define RTC_SEC_MAX_VAL 0xFFFFFFFF
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struct xlnx_rtc_dev {
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struct rtc_device *rtc;
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void __iomem *reg_base;
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int alarm_irq;
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int sec_irq;
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};
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static int xlnx_rtc_set_time(struct device *dev, struct rtc_time *tm)
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{
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struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
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unsigned long new_time;
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new_time = rtc_tm_to_time64(tm);
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if (new_time > RTC_SEC_MAX_VAL)
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return -EINVAL;
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writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR);
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return 0;
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}
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static int xlnx_rtc_read_time(struct device *dev, struct rtc_time *tm)
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{
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struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
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rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_CUR_TM), tm);
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return rtc_valid_tm(tm);
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}
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static int xlnx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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{
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struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
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rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_ALRM), &alrm->time);
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alrm->enabled = readl(xrtcdev->reg_base + RTC_INT_MASK) & RTC_INT_ALRM;
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return 0;
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}
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static int xlnx_rtc_alarm_irq_enable(struct device *dev, u32 enabled)
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{
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struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
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if (enabled)
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writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_EN);
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else
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writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_DIS);
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return 0;
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}
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static int xlnx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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{
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struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
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unsigned long alarm_time;
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alarm_time = rtc_tm_to_time64(&alrm->time);
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if (alarm_time > RTC_SEC_MAX_VAL)
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return -EINVAL;
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writel((u32)alarm_time, (xrtcdev->reg_base + RTC_ALRM));
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xlnx_rtc_alarm_irq_enable(dev, alrm->enabled);
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return 0;
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}
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static void xlnx_init_rtc(struct xlnx_rtc_dev *xrtcdev, u32 calibval)
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{
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/*
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* Based on crystal freq of 33.330 KHz
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* set the seconds counter and enable, set fractions counter
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* to default value suggested as per design spec
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* to correct RTC delay in frequency over period of time.
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*/
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calibval &= RTC_CALIB_MASK;
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writel(calibval, (xrtcdev->reg_base + RTC_CALIB_WR));
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}
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static const struct rtc_class_ops xlnx_rtc_ops = {
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.set_time = xlnx_rtc_set_time,
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.read_time = xlnx_rtc_read_time,
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.read_alarm = xlnx_rtc_read_alarm,
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.set_alarm = xlnx_rtc_set_alarm,
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.alarm_irq_enable = xlnx_rtc_alarm_irq_enable,
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};
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static irqreturn_t xlnx_rtc_interrupt(int irq, void *id)
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{
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struct xlnx_rtc_dev *xrtcdev = (struct xlnx_rtc_dev *)id;
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unsigned int status;
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status = readl(xrtcdev->reg_base + RTC_INT_STS);
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/* Check if interrupt asserted */
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if (!(status & (RTC_INT_SEC | RTC_INT_ALRM)))
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return IRQ_NONE;
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/* Clear interrupt */
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writel(status, xrtcdev->reg_base + RTC_INT_STS);
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if (status & RTC_INT_SEC)
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rtc_update_irq(xrtcdev->rtc, 1, RTC_IRQF | RTC_UF);
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if (status & RTC_INT_ALRM)
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rtc_update_irq(xrtcdev->rtc, 1, RTC_IRQF | RTC_AF);
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return IRQ_HANDLED;
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}
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static int xlnx_rtc_probe(struct platform_device *pdev)
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{
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struct xlnx_rtc_dev *xrtcdev;
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struct resource *res;
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int ret;
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unsigned int calibvalue;
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xrtcdev = devm_kzalloc(&pdev->dev, sizeof(*xrtcdev), GFP_KERNEL);
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if (!xrtcdev)
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return -ENOMEM;
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platform_set_drvdata(pdev, xrtcdev);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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xrtcdev->reg_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(xrtcdev->reg_base))
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return PTR_ERR(xrtcdev->reg_base);
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xrtcdev->alarm_irq = platform_get_irq_byname(pdev, "alarm");
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if (xrtcdev->alarm_irq < 0) {
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dev_err(&pdev->dev, "no irq resource\n");
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return xrtcdev->alarm_irq;
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}
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ret = devm_request_irq(&pdev->dev, xrtcdev->alarm_irq,
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xlnx_rtc_interrupt, 0,
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dev_name(&pdev->dev), xrtcdev);
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if (ret) {
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dev_err(&pdev->dev, "request irq failed\n");
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return ret;
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}
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xrtcdev->sec_irq = platform_get_irq_byname(pdev, "sec");
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if (xrtcdev->sec_irq < 0) {
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dev_err(&pdev->dev, "no irq resource\n");
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return xrtcdev->sec_irq;
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}
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ret = devm_request_irq(&pdev->dev, xrtcdev->sec_irq,
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xlnx_rtc_interrupt, 0,
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dev_name(&pdev->dev), xrtcdev);
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if (ret) {
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dev_err(&pdev->dev, "request irq failed\n");
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return ret;
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}
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ret = of_property_read_u32(pdev->dev.of_node, "calibration",
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&calibvalue);
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if (ret)
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calibvalue = RTC_CALIB_DEF;
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xlnx_init_rtc(xrtcdev, calibvalue);
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device_init_wakeup(&pdev->dev, 1);
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xrtcdev->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
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&xlnx_rtc_ops, THIS_MODULE);
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return PTR_ERR_OR_ZERO(xrtcdev->rtc);
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}
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static int xlnx_rtc_remove(struct platform_device *pdev)
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{
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xlnx_rtc_alarm_irq_enable(&pdev->dev, 0);
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device_init_wakeup(&pdev->dev, 0);
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return 0;
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}
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static int __maybe_unused xlnx_rtc_suspend(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct xlnx_rtc_dev *xrtcdev = platform_get_drvdata(pdev);
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if (device_may_wakeup(&pdev->dev))
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enable_irq_wake(xrtcdev->alarm_irq);
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else
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xlnx_rtc_alarm_irq_enable(dev, 0);
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return 0;
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}
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static int __maybe_unused xlnx_rtc_resume(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct xlnx_rtc_dev *xrtcdev = platform_get_drvdata(pdev);
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if (device_may_wakeup(&pdev->dev))
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disable_irq_wake(xrtcdev->alarm_irq);
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else
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xlnx_rtc_alarm_irq_enable(dev, 1);
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return 0;
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}
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static SIMPLE_DEV_PM_OPS(xlnx_rtc_pm_ops, xlnx_rtc_suspend, xlnx_rtc_resume);
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static const struct of_device_id xlnx_rtc_of_match[] = {
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{.compatible = "xlnx,zynqmp-rtc" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, xlnx_rtc_of_match);
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static struct platform_driver xlnx_rtc_driver = {
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.probe = xlnx_rtc_probe,
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.remove = xlnx_rtc_remove,
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.driver = {
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.name = KBUILD_MODNAME,
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.pm = &xlnx_rtc_pm_ops,
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.of_match_table = xlnx_rtc_of_match,
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},
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};
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module_platform_driver(xlnx_rtc_driver);
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MODULE_DESCRIPTION("Xilinx Zynq MPSoC RTC driver");
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MODULE_AUTHOR("Xilinx Inc.");
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MODULE_LICENSE("GPL v2");
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