counter: 104-quad-8: Replace mutex with spinlock
This patch replaces the mutex I/O lock with a spinlock. This is in preparation for a subsequent patch adding IRQ support for 104-QUAD-8 devices; we can't sleep in an interrupt context, so we'll need to use a spinlock instead. Acked-by: Syed Nayyar Waris <syednwaris@gmail.com> Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com> Link: https://lore.kernel.org/r/3f74491dec66de10d062978bcb7b9c2b3bdea86c.1632884256.git.vilhelm.gray@gmail.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This commit is contained in:
William Breathitt Gray
Jonathan Cameron
parent
feff17a550
commit
09db4678bf
@ -16,6 +16,7 @@
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/types.h>
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#include <linux/spinlock.h>
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#define QUAD8_EXTENT 32
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@ -43,7 +44,7 @@ MODULE_PARM_DESC(base, "ACCES 104-QUAD-8 base addresses");
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* @base: base port address of the device
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*/
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struct quad8 {
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struct mutex lock;
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spinlock_t lock;
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struct counter_device counter;
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unsigned int fck_prescaler[QUAD8_NUM_COUNTERS];
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unsigned int preset[QUAD8_NUM_COUNTERS];
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@ -124,6 +125,7 @@ static int quad8_count_read(struct counter_device *counter,
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unsigned int flags;
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unsigned int borrow;
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unsigned int carry;
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unsigned long irqflags;
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int i;
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flags = inb(base_offset + 1);
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@ -133,7 +135,7 @@ static int quad8_count_read(struct counter_device *counter,
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/* Borrow XOR Carry effectively doubles count range */
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*val = (unsigned long)(borrow ^ carry) << 24;
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mutex_lock(&priv->lock);
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spin_lock_irqsave(&priv->lock, irqflags);
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/* Reset Byte Pointer; transfer Counter to Output Latch */
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outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT,
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@ -142,7 +144,7 @@ static int quad8_count_read(struct counter_device *counter,
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for (i = 0; i < 3; i++)
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*val |= (unsigned long)inb(base_offset) << (8 * i);
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mutex_unlock(&priv->lock);
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spin_unlock_irqrestore(&priv->lock, irqflags);
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return 0;
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}
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@ -152,13 +154,14 @@ static int quad8_count_write(struct counter_device *counter,
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{
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struct quad8 *const priv = counter->priv;
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const int base_offset = priv->base + 2 * count->id;
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unsigned long irqflags;
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int i;
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/* Only 24-bit values are supported */
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if (val > 0xFFFFFF)
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return -ERANGE;
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mutex_lock(&priv->lock);
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spin_lock_irqsave(&priv->lock, irqflags);
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/* Reset Byte Pointer */
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outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
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@ -183,7 +186,7 @@ static int quad8_count_write(struct counter_device *counter,
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/* Reset Error flag */
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outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1);
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mutex_unlock(&priv->lock);
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spin_unlock_irqrestore(&priv->lock, irqflags);
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return 0;
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}
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@ -201,8 +204,9 @@ static int quad8_function_read(struct counter_device *counter,
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{
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struct quad8 *const priv = counter->priv;
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const int id = count->id;
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unsigned long irqflags;
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mutex_lock(&priv->lock);
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spin_lock_irqsave(&priv->lock, irqflags);
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if (priv->quadrature_mode[id])
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switch (priv->quadrature_scale[id]) {
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@ -219,7 +223,7 @@ static int quad8_function_read(struct counter_device *counter,
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else
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*function = COUNTER_FUNCTION_PULSE_DIRECTION;
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mutex_unlock(&priv->lock);
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spin_unlock_irqrestore(&priv->lock, irqflags);
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return 0;
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}
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@ -234,10 +238,11 @@ static int quad8_function_write(struct counter_device *counter,
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unsigned int *const scale = priv->quadrature_scale + id;
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unsigned int *const synchronous_mode = priv->synchronous_mode + id;
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const int base_offset = priv->base + 2 * id + 1;
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unsigned long irqflags;
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unsigned int mode_cfg;
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unsigned int idr_cfg;
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mutex_lock(&priv->lock);
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spin_lock_irqsave(&priv->lock, irqflags);
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mode_cfg = priv->count_mode[id] << 1;
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idr_cfg = priv->index_polarity[id] << 1;
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@ -272,7 +277,7 @@ static int quad8_function_write(struct counter_device *counter,
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break;
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default:
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/* should never reach this path */
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mutex_unlock(&priv->lock);
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spin_unlock_irqrestore(&priv->lock, irqflags);
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return -EINVAL;
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}
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}
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@ -280,7 +285,7 @@ static int quad8_function_write(struct counter_device *counter,
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/* Load mode configuration to Counter Mode Register */
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outb(QUAD8_CTR_CMR | mode_cfg, base_offset);
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mutex_unlock(&priv->lock);
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spin_unlock_irqrestore(&priv->lock, irqflags);
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return 0;
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}
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@ -406,9 +411,10 @@ static int quad8_index_polarity_set(struct counter_device *counter,
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struct quad8 *const priv = counter->priv;
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const size_t channel_id = signal->id - 16;
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const int base_offset = priv->base + 2 * channel_id + 1;
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unsigned long irqflags;
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unsigned int idr_cfg = index_polarity << 1;
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mutex_lock(&priv->lock);
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spin_lock_irqsave(&priv->lock, irqflags);
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idr_cfg |= priv->synchronous_mode[channel_id];
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@ -417,7 +423,7 @@ static int quad8_index_polarity_set(struct counter_device *counter,
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/* Load Index Control configuration to Index Control Register */
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outb(QUAD8_CTR_IDR | idr_cfg, base_offset);
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mutex_unlock(&priv->lock);
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spin_unlock_irqrestore(&priv->lock, irqflags);
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return 0;
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}
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@ -446,15 +452,16 @@ static int quad8_synchronous_mode_set(struct counter_device *counter,
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struct quad8 *const priv = counter->priv;
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const size_t channel_id = signal->id - 16;
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const int base_offset = priv->base + 2 * channel_id + 1;
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unsigned long irqflags;
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unsigned int idr_cfg = synchronous_mode;
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mutex_lock(&priv->lock);
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spin_lock_irqsave(&priv->lock, irqflags);
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idr_cfg |= priv->index_polarity[channel_id] << 1;
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/* Index function must be non-synchronous in non-quadrature mode */
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if (synchronous_mode && !priv->quadrature_mode[channel_id]) {
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mutex_unlock(&priv->lock);
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spin_unlock_irqrestore(&priv->lock, irqflags);
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return -EINVAL;
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}
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@ -463,7 +470,7 @@ static int quad8_synchronous_mode_set(struct counter_device *counter,
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/* Load Index Control configuration to Index Control Register */
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outb(QUAD8_CTR_IDR | idr_cfg, base_offset);
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mutex_unlock(&priv->lock);
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spin_unlock_irqrestore(&priv->lock, irqflags);
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return 0;
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}
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@ -510,6 +517,7 @@ static int quad8_count_mode_write(struct counter_device *counter,
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unsigned int count_mode;
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unsigned int mode_cfg;
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const int base_offset = priv->base + 2 * count->id + 1;
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unsigned long irqflags;
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/* Map Generic Counter count mode to 104-QUAD-8 count mode */
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switch (cnt_mode) {
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@ -530,7 +538,7 @@ static int quad8_count_mode_write(struct counter_device *counter,
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return -EINVAL;
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}
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mutex_lock(&priv->lock);
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spin_lock_irqsave(&priv->lock, irqflags);
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priv->count_mode[count->id] = count_mode;
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@ -544,7 +552,7 @@ static int quad8_count_mode_write(struct counter_device *counter,
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/* Load mode configuration to Counter Mode Register */
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outb(QUAD8_CTR_CMR | mode_cfg, base_offset);
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mutex_unlock(&priv->lock);
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spin_unlock_irqrestore(&priv->lock, irqflags);
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return 0;
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}
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@ -564,9 +572,10 @@ static int quad8_count_enable_write(struct counter_device *counter,
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{
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struct quad8 *const priv = counter->priv;
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const int base_offset = priv->base + 2 * count->id;
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unsigned long irqflags;
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unsigned int ior_cfg;
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mutex_lock(&priv->lock);
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spin_lock_irqsave(&priv->lock, irqflags);
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priv->ab_enable[count->id] = enable;
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@ -575,7 +584,7 @@ static int quad8_count_enable_write(struct counter_device *counter,
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/* Load I/O control configuration */
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outb(QUAD8_CTR_IOR | ior_cfg, base_offset + 1);
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mutex_unlock(&priv->lock);
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spin_unlock_irqrestore(&priv->lock, irqflags);
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return 0;
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}
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@ -626,16 +635,17 @@ static int quad8_count_preset_write(struct counter_device *counter,
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struct counter_count *count, u64 preset)
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{
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struct quad8 *const priv = counter->priv;
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unsigned long irqflags;
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/* Only 24-bit values are supported */
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if (preset > 0xFFFFFF)
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return -ERANGE;
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mutex_lock(&priv->lock);
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spin_lock_irqsave(&priv->lock, irqflags);
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quad8_preset_register_set(priv, count->id, preset);
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mutex_unlock(&priv->lock);
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spin_unlock_irqrestore(&priv->lock, irqflags);
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return 0;
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}
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@ -644,8 +654,9 @@ static int quad8_count_ceiling_read(struct counter_device *counter,
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struct counter_count *count, u64 *ceiling)
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{
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struct quad8 *const priv = counter->priv;
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unsigned long irqflags;
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mutex_lock(&priv->lock);
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spin_lock_irqsave(&priv->lock, irqflags);
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/* Range Limit and Modulo-N count modes use preset value as ceiling */
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switch (priv->count_mode[count->id]) {
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@ -659,7 +670,7 @@ static int quad8_count_ceiling_read(struct counter_device *counter,
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break;
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}
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mutex_unlock(&priv->lock);
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spin_unlock_irqrestore(&priv->lock, irqflags);
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return 0;
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}
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@ -668,23 +679,24 @@ static int quad8_count_ceiling_write(struct counter_device *counter,
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struct counter_count *count, u64 ceiling)
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{
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struct quad8 *const priv = counter->priv;
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unsigned long irqflags;
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/* Only 24-bit values are supported */
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if (ceiling > 0xFFFFFF)
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return -ERANGE;
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mutex_lock(&priv->lock);
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spin_lock_irqsave(&priv->lock, irqflags);
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/* Range Limit and Modulo-N count modes use preset value as ceiling */
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switch (priv->count_mode[count->id]) {
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case 1:
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case 3:
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quad8_preset_register_set(priv, count->id, ceiling);
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mutex_unlock(&priv->lock);
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spin_unlock_irqrestore(&priv->lock, irqflags);
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return 0;
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}
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mutex_unlock(&priv->lock);
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spin_unlock_irqrestore(&priv->lock, irqflags);
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return -EINVAL;
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}
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@ -706,12 +718,13 @@ static int quad8_count_preset_enable_write(struct counter_device *counter,
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{
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struct quad8 *const priv = counter->priv;
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const int base_offset = priv->base + 2 * count->id + 1;
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unsigned long irqflags;
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unsigned int ior_cfg;
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/* Preset enable is active low in Input/Output Control register */
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preset_enable = !preset_enable;
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mutex_lock(&priv->lock);
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spin_lock_irqsave(&priv->lock, irqflags);
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priv->preset_enable[count->id] = preset_enable;
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@ -720,7 +733,7 @@ static int quad8_count_preset_enable_write(struct counter_device *counter,
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/* Load I/O control configuration to Input / Output Control Register */
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outb(QUAD8_CTR_IOR | ior_cfg, base_offset);
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mutex_unlock(&priv->lock);
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spin_unlock_irqrestore(&priv->lock, irqflags);
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return 0;
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}
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@ -731,22 +744,23 @@ static int quad8_signal_cable_fault_read(struct counter_device *counter,
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{
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struct quad8 *const priv = counter->priv;
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const size_t channel_id = signal->id / 2;
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unsigned long irqflags;
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bool disabled;
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unsigned int status;
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mutex_lock(&priv->lock);
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spin_lock_irqsave(&priv->lock, irqflags);
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disabled = !(priv->cable_fault_enable & BIT(channel_id));
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if (disabled) {
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mutex_unlock(&priv->lock);
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spin_unlock_irqrestore(&priv->lock, irqflags);
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return -EINVAL;
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}
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/* Logic 0 = cable fault */
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status = inb(priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS);
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mutex_unlock(&priv->lock);
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spin_unlock_irqrestore(&priv->lock, irqflags);
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/* Mask respective channel and invert logic */
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*cable_fault = !(status & BIT(channel_id));
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@ -772,9 +786,10 @@ static int quad8_signal_cable_fault_enable_write(struct counter_device *counter,
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{
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struct quad8 *const priv = counter->priv;
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const size_t channel_id = signal->id / 2;
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unsigned long irqflags;
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unsigned int cable_fault_enable;
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mutex_lock(&priv->lock);
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spin_lock_irqsave(&priv->lock, irqflags);
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if (enable)
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priv->cable_fault_enable |= BIT(channel_id);
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@ -786,7 +801,7 @@ static int quad8_signal_cable_fault_enable_write(struct counter_device *counter,
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outb(cable_fault_enable, priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS);
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mutex_unlock(&priv->lock);
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spin_unlock_irqrestore(&priv->lock, irqflags);
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return 0;
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}
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@ -809,8 +824,9 @@ static int quad8_signal_fck_prescaler_write(struct counter_device *counter,
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struct quad8 *const priv = counter->priv;
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const size_t channel_id = signal->id / 2;
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const int base_offset = priv->base + 2 * channel_id;
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unsigned long irqflags;
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mutex_lock(&priv->lock);
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spin_lock_irqsave(&priv->lock, irqflags);
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priv->fck_prescaler[channel_id] = prescaler;
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@ -822,7 +838,7 @@ static int quad8_signal_fck_prescaler_write(struct counter_device *counter,
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outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC,
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base_offset + 1);
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mutex_unlock(&priv->lock);
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spin_unlock_irqrestore(&priv->lock, irqflags);
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return 0;
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}
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@ -991,8 +1007,7 @@ static int quad8_probe(struct device *dev, unsigned int id)
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priv->counter.priv = priv;
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priv->base = base[id];
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/* Initialize mutex */
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mutex_init(&priv->lock);
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spin_lock_init(&priv->lock);
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/* Reset all counters and disable interrupt function */
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outb(QUAD8_CHAN_OP_RESET_COUNTERS, base[id] + QUAD8_REG_CHAN_OP);
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