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drm/amdgpu: set CPU mapping of vram as cached for A+A mode

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New A+A HW supports cached vram mapped to cpu.

Signed-off-by: Eric Huang <jinhuieric.huang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Eric Huang
2021-02-27 16:51:19 -05:00
committed by Alex Deucher
parent 761d86d37f
commit 06bfc045d5
1 changed files with 4 additions and 1 deletions
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5
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
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@@ -673,7 +673,10 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_reso
mem->bus.offset += adev->gmc.aper_base;
mem->bus.is_iomem = true;
mem->bus.caching = ttm_write_combined;
if (adev->gmc.xgmi.connected_to_cpu)
mem->bus.caching = ttm_cached;
else
mem->bus.caching = ttm_write_combined;
break;
default:
return -EINVAL;