forked from Minki/linux
[ARM] pxa: move UART register definitions into dedicated regs-uart.h
Signed-off-by: Eric Miao <eric.miao@marvell.com>
This commit is contained in:
parent
b31eca4f00
commit
02f652626a
@ -156,8 +156,8 @@ void __init set_pxa_fb_parent(struct device *parent_dev)
|
||||
|
||||
static struct resource pxa_resource_ffuart[] = {
|
||||
{
|
||||
.start = __PREG(FFUART),
|
||||
.end = __PREG(FFUART) + 35,
|
||||
.start = 0x40100000,
|
||||
.end = 0x40100023,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = IRQ_FFUART,
|
||||
@ -175,8 +175,8 @@ struct platform_device pxa_device_ffuart= {
|
||||
|
||||
static struct resource pxa_resource_btuart[] = {
|
||||
{
|
||||
.start = __PREG(BTUART),
|
||||
.end = __PREG(BTUART) + 35,
|
||||
.start = 0x40200000,
|
||||
.end = 0x40200023,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = IRQ_BTUART,
|
||||
@ -194,8 +194,8 @@ struct platform_device pxa_device_btuart = {
|
||||
|
||||
static struct resource pxa_resource_stuart[] = {
|
||||
{
|
||||
.start = __PREG(STUART),
|
||||
.end = __PREG(STUART) + 35,
|
||||
.start = 0x40700000,
|
||||
.end = 0x40700023,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = IRQ_STUART,
|
||||
@ -213,8 +213,8 @@ struct platform_device pxa_device_stuart = {
|
||||
|
||||
static struct resource pxa_resource_hwuart[] = {
|
||||
{
|
||||
.start = __PREG(HWUART),
|
||||
.end = __PREG(HWUART) + 47,
|
||||
.start = 0x41600000,
|
||||
.end = 0x4160002F,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = IRQ_HWUART,
|
||||
|
@ -123,147 +123,6 @@
|
||||
#define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */
|
||||
#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
|
||||
|
||||
|
||||
/*
|
||||
* UARTs
|
||||
*/
|
||||
|
||||
/* Full Function UART (FFUART) */
|
||||
#define FFUART FFRBR
|
||||
#define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */
|
||||
#define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */
|
||||
#define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */
|
||||
#define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */
|
||||
#define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */
|
||||
#define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */
|
||||
#define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */
|
||||
#define FFLSR __REG(0x40100014) /* Line Status Register (read only) */
|
||||
#define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */
|
||||
#define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */
|
||||
#define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */
|
||||
#define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
|
||||
#define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
|
||||
|
||||
/* Bluetooth UART (BTUART) */
|
||||
#define BTUART BTRBR
|
||||
#define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */
|
||||
#define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */
|
||||
#define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */
|
||||
#define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */
|
||||
#define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */
|
||||
#define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */
|
||||
#define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */
|
||||
#define BTLSR __REG(0x40200014) /* Line Status Register (read only) */
|
||||
#define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */
|
||||
#define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */
|
||||
#define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */
|
||||
#define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
|
||||
#define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
|
||||
|
||||
/* Standard UART (STUART) */
|
||||
#define STUART STRBR
|
||||
#define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */
|
||||
#define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */
|
||||
#define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */
|
||||
#define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */
|
||||
#define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */
|
||||
#define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */
|
||||
#define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */
|
||||
#define STLSR __REG(0x40700014) /* Line Status Register (read only) */
|
||||
#define STMSR __REG(0x40700018) /* Reserved */
|
||||
#define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */
|
||||
#define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */
|
||||
#define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
|
||||
#define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
|
||||
|
||||
/* Hardware UART (HWUART) */
|
||||
#define HWUART HWRBR
|
||||
#define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */
|
||||
#define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */
|
||||
#define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */
|
||||
#define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */
|
||||
#define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */
|
||||
#define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */
|
||||
#define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */
|
||||
#define HWLSR __REG(0x41600014) /* Line Status Register (read only) */
|
||||
#define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */
|
||||
#define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */
|
||||
#define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */
|
||||
#define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */
|
||||
#define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */
|
||||
#define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */
|
||||
#define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
|
||||
#define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
|
||||
|
||||
#define IER_DMAE (1 << 7) /* DMA Requests Enable */
|
||||
#define IER_UUE (1 << 6) /* UART Unit Enable */
|
||||
#define IER_NRZE (1 << 5) /* NRZ coding Enable */
|
||||
#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */
|
||||
#define IER_MIE (1 << 3) /* Modem Interrupt Enable */
|
||||
#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */
|
||||
#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */
|
||||
#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */
|
||||
|
||||
#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */
|
||||
#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */
|
||||
#define IIR_TOD (1 << 3) /* Time Out Detected */
|
||||
#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */
|
||||
#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */
|
||||
#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */
|
||||
|
||||
#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */
|
||||
#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */
|
||||
#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */
|
||||
#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */
|
||||
#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */
|
||||
#define FCR_ITL_1 (0)
|
||||
#define FCR_ITL_8 (FCR_ITL1)
|
||||
#define FCR_ITL_16 (FCR_ITL2)
|
||||
#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
|
||||
|
||||
#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */
|
||||
#define LCR_SB (1 << 6) /* Set Break */
|
||||
#define LCR_STKYP (1 << 5) /* Sticky Parity */
|
||||
#define LCR_EPS (1 << 4) /* Even Parity Select */
|
||||
#define LCR_PEN (1 << 3) /* Parity Enable */
|
||||
#define LCR_STB (1 << 2) /* Stop Bit */
|
||||
#define LCR_WLS1 (1 << 1) /* Word Length Select */
|
||||
#define LCR_WLS0 (1 << 0) /* Word Length Select */
|
||||
|
||||
#define LSR_FIFOE (1 << 7) /* FIFO Error Status */
|
||||
#define LSR_TEMT (1 << 6) /* Transmitter Empty */
|
||||
#define LSR_TDRQ (1 << 5) /* Transmit Data Request */
|
||||
#define LSR_BI (1 << 4) /* Break Interrupt */
|
||||
#define LSR_FE (1 << 3) /* Framing Error */
|
||||
#define LSR_PE (1 << 2) /* Parity Error */
|
||||
#define LSR_OE (1 << 1) /* Overrun Error */
|
||||
#define LSR_DR (1 << 0) /* Data Ready */
|
||||
|
||||
#define MCR_LOOP (1 << 4)
|
||||
#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
|
||||
#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
|
||||
#define MCR_RTS (1 << 1) /* Request to Send */
|
||||
#define MCR_DTR (1 << 0) /* Data Terminal Ready */
|
||||
|
||||
#define MSR_DCD (1 << 7) /* Data Carrier Detect */
|
||||
#define MSR_RI (1 << 6) /* Ring Indicator */
|
||||
#define MSR_DSR (1 << 5) /* Data Set Ready */
|
||||
#define MSR_CTS (1 << 4) /* Clear To Send */
|
||||
#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */
|
||||
#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */
|
||||
#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
|
||||
#define MSR_DCTS (1 << 0) /* Delta Clear To Send */
|
||||
|
||||
/*
|
||||
* IrSR (Infrared Selection Register)
|
||||
*/
|
||||
#define STISR_RXPL (1 << 4) /* Receive Data Polarity */
|
||||
#define STISR_TXPL (1 << 3) /* Transmit Data Polarity */
|
||||
#define STISR_XMODE (1 << 2) /* Transmit Pulse Width Select */
|
||||
#define STISR_RCVEIR (1 << 1) /* Receiver SIR Enable */
|
||||
#define STISR_XMITIR (1 << 0) /* Transmitter SIR Enable */
|
||||
|
||||
|
||||
/*
|
||||
* I2C registers - moved into drivers/i2c/busses/i2c-pxa.c
|
||||
*/
|
||||
|
143
arch/arm/mach-pxa/include/mach/regs-uart.h
Normal file
143
arch/arm/mach-pxa/include/mach/regs-uart.h
Normal file
@ -0,0 +1,143 @@
|
||||
#ifndef __ASM_ARCH_REGS_UART_H
|
||||
#define __ASM_ARCH_REGS_UART_H
|
||||
|
||||
/*
|
||||
* UARTs
|
||||
*/
|
||||
|
||||
/* Full Function UART (FFUART) */
|
||||
#define FFUART FFRBR
|
||||
#define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */
|
||||
#define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */
|
||||
#define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */
|
||||
#define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */
|
||||
#define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */
|
||||
#define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */
|
||||
#define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */
|
||||
#define FFLSR __REG(0x40100014) /* Line Status Register (read only) */
|
||||
#define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */
|
||||
#define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */
|
||||
#define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */
|
||||
#define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
|
||||
#define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
|
||||
|
||||
/* Bluetooth UART (BTUART) */
|
||||
#define BTUART BTRBR
|
||||
#define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */
|
||||
#define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */
|
||||
#define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */
|
||||
#define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */
|
||||
#define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */
|
||||
#define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */
|
||||
#define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */
|
||||
#define BTLSR __REG(0x40200014) /* Line Status Register (read only) */
|
||||
#define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */
|
||||
#define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */
|
||||
#define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */
|
||||
#define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
|
||||
#define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
|
||||
|
||||
/* Standard UART (STUART) */
|
||||
#define STUART STRBR
|
||||
#define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */
|
||||
#define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */
|
||||
#define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */
|
||||
#define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */
|
||||
#define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */
|
||||
#define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */
|
||||
#define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */
|
||||
#define STLSR __REG(0x40700014) /* Line Status Register (read only) */
|
||||
#define STMSR __REG(0x40700018) /* Reserved */
|
||||
#define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */
|
||||
#define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */
|
||||
#define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
|
||||
#define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
|
||||
|
||||
/* Hardware UART (HWUART) */
|
||||
#define HWUART HWRBR
|
||||
#define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */
|
||||
#define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */
|
||||
#define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */
|
||||
#define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */
|
||||
#define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */
|
||||
#define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */
|
||||
#define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */
|
||||
#define HWLSR __REG(0x41600014) /* Line Status Register (read only) */
|
||||
#define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */
|
||||
#define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */
|
||||
#define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */
|
||||
#define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */
|
||||
#define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */
|
||||
#define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */
|
||||
#define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
|
||||
#define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
|
||||
|
||||
#define IER_DMAE (1 << 7) /* DMA Requests Enable */
|
||||
#define IER_UUE (1 << 6) /* UART Unit Enable */
|
||||
#define IER_NRZE (1 << 5) /* NRZ coding Enable */
|
||||
#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */
|
||||
#define IER_MIE (1 << 3) /* Modem Interrupt Enable */
|
||||
#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */
|
||||
#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */
|
||||
#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */
|
||||
|
||||
#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */
|
||||
#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */
|
||||
#define IIR_TOD (1 << 3) /* Time Out Detected */
|
||||
#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */
|
||||
#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */
|
||||
#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */
|
||||
|
||||
#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */
|
||||
#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */
|
||||
#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */
|
||||
#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */
|
||||
#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */
|
||||
#define FCR_ITL_1 (0)
|
||||
#define FCR_ITL_8 (FCR_ITL1)
|
||||
#define FCR_ITL_16 (FCR_ITL2)
|
||||
#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
|
||||
|
||||
#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */
|
||||
#define LCR_SB (1 << 6) /* Set Break */
|
||||
#define LCR_STKYP (1 << 5) /* Sticky Parity */
|
||||
#define LCR_EPS (1 << 4) /* Even Parity Select */
|
||||
#define LCR_PEN (1 << 3) /* Parity Enable */
|
||||
#define LCR_STB (1 << 2) /* Stop Bit */
|
||||
#define LCR_WLS1 (1 << 1) /* Word Length Select */
|
||||
#define LCR_WLS0 (1 << 0) /* Word Length Select */
|
||||
|
||||
#define LSR_FIFOE (1 << 7) /* FIFO Error Status */
|
||||
#define LSR_TEMT (1 << 6) /* Transmitter Empty */
|
||||
#define LSR_TDRQ (1 << 5) /* Transmit Data Request */
|
||||
#define LSR_BI (1 << 4) /* Break Interrupt */
|
||||
#define LSR_FE (1 << 3) /* Framing Error */
|
||||
#define LSR_PE (1 << 2) /* Parity Error */
|
||||
#define LSR_OE (1 << 1) /* Overrun Error */
|
||||
#define LSR_DR (1 << 0) /* Data Ready */
|
||||
|
||||
#define MCR_LOOP (1 << 4)
|
||||
#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
|
||||
#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
|
||||
#define MCR_RTS (1 << 1) /* Request to Send */
|
||||
#define MCR_DTR (1 << 0) /* Data Terminal Ready */
|
||||
|
||||
#define MSR_DCD (1 << 7) /* Data Carrier Detect */
|
||||
#define MSR_RI (1 << 6) /* Ring Indicator */
|
||||
#define MSR_DSR (1 << 5) /* Data Set Ready */
|
||||
#define MSR_CTS (1 << 4) /* Clear To Send */
|
||||
#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */
|
||||
#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */
|
||||
#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
|
||||
#define MSR_DCTS (1 << 0) /* Delta Clear To Send */
|
||||
|
||||
/*
|
||||
* IrSR (Infrared Selection Register)
|
||||
*/
|
||||
#define STISR_RXPL (1 << 4) /* Receive Data Polarity */
|
||||
#define STISR_TXPL (1 << 3) /* Transmit Data Polarity */
|
||||
#define STISR_XMODE (1 << 2) /* Transmit Pulse Width Select */
|
||||
#define STISR_RCVEIR (1 << 1) /* Receiver SIR Enable */
|
||||
#define STISR_XMITIR (1 << 0) /* Transmitter SIR Enable */
|
||||
|
||||
#endif /* __ASM_ARCH_REGS_UART_H */
|
@ -10,7 +10,7 @@
|
||||
*/
|
||||
|
||||
#include <linux/serial_reg.h>
|
||||
#include <mach/pxa-regs.h>
|
||||
#include <mach/regs-uart.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#define __REG(x) ((volatile unsigned long *)x)
|
||||
|
@ -25,6 +25,7 @@
|
||||
#include <asm/dma.h>
|
||||
#include <mach/irda.h>
|
||||
#include <mach/pxa-regs.h>
|
||||
#include <mach/regs-uart.h>
|
||||
|
||||
#define FICP __REG(0x40800000) /* Start of FICP area */
|
||||
#define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */
|
||||
|
@ -48,6 +48,7 @@
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/irq.h>
|
||||
#include <mach/pxa-regs.h>
|
||||
#include <mach/regs-uart.h>
|
||||
|
||||
|
||||
struct uart_pxa_port {
|
||||
|
Loading…
Reference in New Issue
Block a user