forked from Minki/linux
Merge remote-tracking branches 'asoc/topic/wm8741', 'asoc/topic/wm8753', 'asoc/topic/wm8904', 'asoc/topic/wm8960' and 'asoc/topic/wm8983' into asoc-next
This commit is contained in:
Mark Brown
commit
02dc14d66e
@ -61,25 +61,6 @@ static const struct reg_default wm8741_reg_defaults[] = {
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{ 32, 0x0002 }, /* R32 - ADDITONAL_CONTROL_1 */
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};
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static bool wm8741_readable(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case WM8741_DACLLSB_ATTENUATION:
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case WM8741_DACLMSB_ATTENUATION:
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case WM8741_DACRLSB_ATTENUATION:
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case WM8741_DACRMSB_ATTENUATION:
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case WM8741_VOLUME_CONTROL:
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case WM8741_FORMAT_CONTROL:
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case WM8741_FILTER_CONTROL:
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case WM8741_MODE_CONTROL_1:
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case WM8741_MODE_CONTROL_2:
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case WM8741_ADDITIONAL_CONTROL_1:
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return true;
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default:
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return false;
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}
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}
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static int wm8741_reset(struct snd_soc_codec *codec)
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{
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return snd_soc_write(codec, WM8741_RESET, 0);
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@ -278,51 +259,38 @@ static int wm8741_set_dai_sysclk(struct snd_soc_dai *codec_dai,
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switch (freq) {
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case 0:
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wm8741->sysclk_constraints = NULL;
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wm8741->sysclk = freq;
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return 0;
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break;
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case 11289600:
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wm8741->sysclk_constraints = &constraints_11289;
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wm8741->sysclk = freq;
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return 0;
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break;
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case 12288000:
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wm8741->sysclk_constraints = &constraints_12288;
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wm8741->sysclk = freq;
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return 0;
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break;
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case 16384000:
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wm8741->sysclk_constraints = &constraints_16384;
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wm8741->sysclk = freq;
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return 0;
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break;
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case 16934400:
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wm8741->sysclk_constraints = &constraints_16934;
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wm8741->sysclk = freq;
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return 0;
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break;
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case 18432000:
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wm8741->sysclk_constraints = &constraints_18432;
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wm8741->sysclk = freq;
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return 0;
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break;
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case 22579200:
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case 33868800:
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wm8741->sysclk_constraints = &constraints_22579;
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wm8741->sysclk = freq;
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return 0;
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break;
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case 24576000:
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wm8741->sysclk_constraints = &constraints_24576;
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wm8741->sysclk = freq;
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return 0;
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break;
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case 36864000:
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wm8741->sysclk_constraints = &constraints_36864;
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wm8741->sysclk = freq;
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return 0;
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break;
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default:
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return -EINVAL;
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}
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return -EINVAL;
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wm8741->sysclk = freq;
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return 0;
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}
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static int wm8741_set_dai_fmt(struct snd_soc_dai *codec_dai,
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@ -554,8 +522,6 @@ static const struct regmap_config wm8741_regmap = {
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.reg_defaults = wm8741_reg_defaults,
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.num_reg_defaults = ARRAY_SIZE(wm8741_reg_defaults),
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.cache_type = REGCACHE_RBTREE,
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.readable_reg = wm8741_readable,
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};
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static int wm8741_set_pdata(struct device *dev, struct wm8741_priv *wm8741)
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@ -138,11 +138,6 @@ static bool wm8753_volatile(struct device *dev, unsigned int reg)
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return reg == WM8753_RESET;
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}
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static bool wm8753_writeable(struct device *dev, unsigned int reg)
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{
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return reg <= WM8753_ADCTL2;
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}
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/* codec private data */
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struct wm8753_priv {
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struct regmap *regmap;
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@ -1509,7 +1504,6 @@ static const struct regmap_config wm8753_regmap = {
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.val_bits = 9,
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.max_register = WM8753_ADCTL2,
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.writeable_reg = wm8753_writeable,
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.volatile_reg = wm8753_volatile,
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.cache_type = REGCACHE_RBTREE,
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@ -1837,7 +1837,9 @@ static int wm8904_set_bias_level(struct snd_soc_codec *codec,
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switch (level) {
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case SND_SOC_BIAS_ON:
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clk_prepare_enable(wm8904->mclk);
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ret = clk_prepare_enable(wm8904->mclk);
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if (ret)
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return ret;
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break;
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case SND_SOC_BIAS_PREPARE:
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@ -48,6 +48,9 @@
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#define WM8960_DISOP 0x40
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#define WM8960_DRES_MASK 0x30
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static bool is_pll_freq_available(unsigned int source, unsigned int target);
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static int wm8960_set_pll(struct snd_soc_codec *codec,
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unsigned int freq_in, unsigned int freq_out);
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/*
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* wm8960 register cache
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* We can't read the WM8960 register space when we are
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@ -126,9 +129,12 @@ struct wm8960_priv {
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struct snd_soc_dapm_widget *rout1;
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struct snd_soc_dapm_widget *out3;
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bool deemph;
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int playback_fs;
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int lrclk;
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int bclk;
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int sysclk;
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int clk_id;
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int freq_in;
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bool is_stream_in_use[2];
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struct wm8960_data pdata;
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};
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@ -164,8 +170,8 @@ static int wm8960_set_deemph(struct snd_soc_codec *codec)
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if (wm8960->deemph) {
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best = 1;
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for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) {
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if (abs(deemph_settings[i] - wm8960->playback_fs) <
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abs(deemph_settings[best] - wm8960->playback_fs))
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if (abs(deemph_settings[i] - wm8960->lrclk) <
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abs(deemph_settings[best] - wm8960->lrclk))
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best = i;
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}
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@ -565,6 +571,9 @@ static struct {
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{ 8000, 5 },
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};
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/* -1 for reserved value */
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static const int sysclk_divs[] = { 1, -1, 2, -1 };
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/* Multiply 256 for internal 256 div */
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static const int dac_divs[] = { 256, 384, 512, 768, 1024, 1408, 1536 };
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@ -574,61 +583,110 @@ static const int bclk_divs[] = {
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120, 160, 220, 240, 320, 320, 320
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};
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static void wm8960_configure_clocking(struct snd_soc_codec *codec,
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bool tx, int lrclk)
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static int wm8960_configure_clocking(struct snd_soc_codec *codec)
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{
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struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
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int sysclk, bclk, lrclk, freq_out, freq_in;
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u16 iface1 = snd_soc_read(codec, WM8960_IFACE1);
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u16 iface2 = snd_soc_read(codec, WM8960_IFACE2);
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u32 sysclk;
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int i, j;
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int i, j, k;
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if (!(iface1 & (1<<6))) {
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dev_dbg(codec->dev,
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"Codec is slave mode, no need to configure clock\n");
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return;
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return 0;
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}
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if (!wm8960->sysclk) {
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dev_dbg(codec->dev, "No SYSCLK configured\n");
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return;
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if (wm8960->clk_id != WM8960_SYSCLK_MCLK && !wm8960->freq_in) {
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dev_err(codec->dev, "No MCLK configured\n");
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return -EINVAL;
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}
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if (!wm8960->bclk || !lrclk) {
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dev_dbg(codec->dev, "No audio clocks configured\n");
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return;
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freq_in = wm8960->freq_in;
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bclk = wm8960->bclk;
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lrclk = wm8960->lrclk;
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/*
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* If it's sysclk auto mode, check if the MCLK can provide sysclk or
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* not. If MCLK can provide sysclk, using MCLK to provide sysclk
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* directly. Otherwise, auto select a available pll out frequency
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* and set PLL.
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*/
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if (wm8960->clk_id == WM8960_SYSCLK_AUTO) {
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/* disable the PLL and using MCLK to provide sysclk */
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wm8960_set_pll(codec, 0, 0);
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freq_out = freq_in;
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} else if (wm8960->sysclk) {
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freq_out = wm8960->sysclk;
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} else {
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dev_err(codec->dev, "No SYSCLK configured\n");
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return -EINVAL;
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}
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for (i = 0; i < ARRAY_SIZE(dac_divs); ++i) {
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if (wm8960->sysclk == lrclk * dac_divs[i]) {
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for (j = 0; j < ARRAY_SIZE(bclk_divs); ++j) {
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sysclk = wm8960->bclk * bclk_divs[j] / 10;
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if (wm8960->sysclk == sysclk)
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/* check if the sysclk frequency is available. */
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for (i = 0; i < ARRAY_SIZE(sysclk_divs); ++i) {
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if (sysclk_divs[i] == -1)
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continue;
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sysclk = freq_out / sysclk_divs[i];
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for (j = 0; j < ARRAY_SIZE(dac_divs); ++j) {
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if (sysclk == dac_divs[j] * lrclk) {
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for (k = 0; k < ARRAY_SIZE(bclk_divs); ++k)
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if (sysclk == bclk * bclk_divs[k] / 10)
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break;
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if (k != ARRAY_SIZE(bclk_divs))
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break;
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}
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if(j != ARRAY_SIZE(bclk_divs))
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}
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if (j != ARRAY_SIZE(dac_divs))
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break;
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}
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if (i != ARRAY_SIZE(sysclk_divs)) {
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goto configure_clock;
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} else if (wm8960->clk_id != WM8960_SYSCLK_AUTO) {
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dev_err(codec->dev, "failed to configure clock\n");
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return -EINVAL;
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}
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/* get a available pll out frequency and set pll */
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for (i = 0; i < ARRAY_SIZE(sysclk_divs); ++i) {
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if (sysclk_divs[i] == -1)
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continue;
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for (j = 0; j < ARRAY_SIZE(dac_divs); ++j) {
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sysclk = lrclk * dac_divs[j];
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freq_out = sysclk * sysclk_divs[i];
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for (k = 0; k < ARRAY_SIZE(bclk_divs); ++k) {
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if (sysclk == bclk * bclk_divs[k] / 10 &&
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is_pll_freq_available(freq_in, freq_out)) {
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wm8960_set_pll(codec,
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freq_in, freq_out);
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break;
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} else {
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continue;
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}
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}
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if (k != ARRAY_SIZE(bclk_divs))
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break;
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}
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if (j != ARRAY_SIZE(dac_divs))
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break;
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}
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if (i == ARRAY_SIZE(dac_divs)) {
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dev_err(codec->dev, "Unsupported sysclk %d\n", wm8960->sysclk);
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return;
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if (i == ARRAY_SIZE(sysclk_divs)) {
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dev_err(codec->dev, "failed to configure clock\n");
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return -EINVAL;
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}
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/*
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* configure frame clock. If ADCLRC configure as GPIO pin, DACLRC
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* pin is used as a frame clock for ADCs and DACs.
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*/
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if (iface2 & (1<<6))
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snd_soc_update_bits(codec, WM8960_CLOCK1, 0x7 << 3, i << 3);
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else if (tx)
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snd_soc_update_bits(codec, WM8960_CLOCK1, 0x7 << 3, i << 3);
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else if (!tx)
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snd_soc_update_bits(codec, WM8960_CLOCK1, 0x7 << 6, i << 6);
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configure_clock:
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/* configure sysclk clock */
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snd_soc_update_bits(codec, WM8960_CLOCK1, 3 << 1, i << 1);
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/* configure frame clock */
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snd_soc_update_bits(codec, WM8960_CLOCK1, 0x7 << 3, j << 3);
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snd_soc_update_bits(codec, WM8960_CLOCK1, 0x7 << 6, j << 6);
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/* configure bit clock */
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snd_soc_update_bits(codec, WM8960_CLOCK2, 0xf, j);
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snd_soc_update_bits(codec, WM8960_CLOCK2, 0xf, k);
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return 0;
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}
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static int wm8960_hw_params(struct snd_pcm_substream *substream,
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@ -667,9 +725,9 @@ static int wm8960_hw_params(struct snd_pcm_substream *substream,
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return -EINVAL;
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}
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wm8960->lrclk = params_rate(params);
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/* Update filters for the new rate */
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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wm8960->playback_fs = params_rate(params);
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if (tx) {
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wm8960_set_deemph(codec);
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} else {
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for (i = 0; i < ARRAY_SIZE(alc_rates); i++)
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@ -682,7 +740,23 @@ static int wm8960_hw_params(struct snd_pcm_substream *substream,
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/* set iface */
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snd_soc_write(codec, WM8960_IFACE1, iface);
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wm8960_configure_clocking(codec, tx, params_rate(params));
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wm8960->is_stream_in_use[tx] = true;
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if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_ON &&
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!wm8960->is_stream_in_use[!tx])
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return wm8960_configure_clocking(codec);
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return 0;
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}
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static int wm8960_hw_free(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct snd_soc_codec *codec = dai->codec;
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struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
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bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
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wm8960->is_stream_in_use[tx] = false;
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return 0;
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}
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@ -702,6 +776,7 @@ static int wm8960_set_bias_level_out3(struct snd_soc_codec *codec,
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enum snd_soc_bias_level level)
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{
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struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
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u16 pm2 = snd_soc_read(codec, WM8960_POWER2);
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int ret;
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switch (level) {
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@ -721,11 +796,22 @@ static int wm8960_set_bias_level_out3(struct snd_soc_codec *codec,
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}
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}
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ret = wm8960_configure_clocking(codec);
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if (ret)
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return ret;
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/* Set VMID to 2x50k */
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snd_soc_update_bits(codec, WM8960_POWER1, 0x180, 0x80);
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break;
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case SND_SOC_BIAS_ON:
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/*
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* If it's sysclk auto mode, and the pll is enabled,
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* disable the pll
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*/
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if (wm8960->clk_id == WM8960_SYSCLK_AUTO && (pm2 & 0x1))
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wm8960_set_pll(codec, 0, 0);
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if (!IS_ERR(wm8960->mclk))
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clk_disable_unprepare(wm8960->mclk);
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break;
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@ -780,6 +866,7 @@ static int wm8960_set_bias_level_capless(struct snd_soc_codec *codec,
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enum snd_soc_bias_level level)
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{
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struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
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u16 pm2 = snd_soc_read(codec, WM8960_POWER2);
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int reg, ret;
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switch (level) {
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@ -831,9 +918,21 @@ static int wm8960_set_bias_level_capless(struct snd_soc_codec *codec,
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return ret;
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}
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}
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ret = wm8960_configure_clocking(codec);
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if (ret)
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return ret;
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break;
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case SND_SOC_BIAS_ON:
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/*
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* If it's sysclk auto mode, and the pll is enabled,
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* disable the pll
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*/
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if (wm8960->clk_id == WM8960_SYSCLK_AUTO && (pm2 & 0x1))
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wm8960_set_pll(codec, 0, 0);
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if (!IS_ERR(wm8960->mclk))
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clk_disable_unprepare(wm8960->mclk);
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@ -892,6 +991,28 @@ struct _pll_div {
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u32 k:24;
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};
|
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static bool is_pll_freq_available(unsigned int source, unsigned int target)
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{
|
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unsigned int Ndiv;
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if (source == 0 || target == 0)
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return false;
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/* Scale up target to PLL operating frequency */
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target *= 4;
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Ndiv = target / source;
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|
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if (Ndiv < 6) {
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source >>= 1;
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Ndiv = target / source;
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}
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if ((Ndiv < 6) || (Ndiv > 12))
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return false;
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|
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return true;
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}
|
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|
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/* The size in bits of the pll divide multiplied by 10
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* to allow rounding later */
|
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#define FIXED_PLL_SIZE ((1 << 24) * 10)
|
||||
@ -943,10 +1064,9 @@ static int pll_factors(unsigned int source, unsigned int target,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int wm8960_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
|
||||
int source, unsigned int freq_in, unsigned int freq_out)
|
||||
static int wm8960_set_pll(struct snd_soc_codec *codec,
|
||||
unsigned int freq_in, unsigned int freq_out)
|
||||
{
|
||||
struct snd_soc_codec *codec = codec_dai->codec;
|
||||
u16 reg;
|
||||
static struct _pll_div pll_div;
|
||||
int ret;
|
||||
@ -986,6 +1106,20 @@ static int wm8960_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int wm8960_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
|
||||
int source, unsigned int freq_in, unsigned int freq_out)
|
||||
{
|
||||
struct snd_soc_codec *codec = codec_dai->codec;
|
||||
struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
|
||||
|
||||
wm8960->freq_in = freq_in;
|
||||
|
||||
if (pll_id == WM8960_SYSCLK_AUTO)
|
||||
return 0;
|
||||
|
||||
return wm8960_set_pll(codec, freq_in, freq_out);
|
||||
}
|
||||
|
||||
static int wm8960_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
|
||||
int div_id, int div)
|
||||
{
|
||||
@ -1043,11 +1177,14 @@ static int wm8960_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
|
||||
snd_soc_update_bits(codec, WM8960_CLOCK1,
|
||||
0x1, WM8960_SYSCLK_PLL);
|
||||
break;
|
||||
case WM8960_SYSCLK_AUTO:
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
wm8960->sysclk = freq;
|
||||
wm8960->clk_id = clk_id;
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -1060,6 +1197,7 @@ static int wm8960_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
|
||||
|
||||
static const struct snd_soc_dai_ops wm8960_dai_ops = {
|
||||
.hw_params = wm8960_hw_params,
|
||||
.hw_free = wm8960_hw_free,
|
||||
.digital_mute = wm8960_mute,
|
||||
.set_fmt = wm8960_set_dai_fmt,
|
||||
.set_clkdiv = wm8960_set_dai_clkdiv,
|
||||
|
||||
@ -82,6 +82,7 @@
|
||||
|
||||
#define WM8960_SYSCLK_MCLK (0 << 0)
|
||||
#define WM8960_SYSCLK_PLL (1 << 0)
|
||||
#define WM8960_SYSCLK_AUTO (2 << 0)
|
||||
|
||||
#define WM8960_DAC_DIV_1 (0 << 3)
|
||||
#define WM8960_DAC_DIV_1_5 (1 << 3)
|
||||
|
||||
@ -84,66 +84,6 @@ static const struct reg_default wm8983_defaults[] = {
|
||||
{ 0x3D, 0x0000 }, /* R61 - BIAS CTRL */
|
||||
};
|
||||
|
||||
static const struct wm8983_reg_access {
|
||||
u16 read; /* Mask of readable bits */
|
||||
u16 write; /* Mask of writable bits */
|
||||
} wm8983_access_masks[WM8983_MAX_REGISTER + 1] = {
|
||||
[0x00] = { 0x0000, 0x01FF }, /* R0 - Software Reset */
|
||||
[0x01] = { 0x0000, 0x01FF }, /* R1 - Power management 1 */
|
||||
[0x02] = { 0x0000, 0x01FF }, /* R2 - Power management 2 */
|
||||
[0x03] = { 0x0000, 0x01EF }, /* R3 - Power management 3 */
|
||||
[0x04] = { 0x0000, 0x01FF }, /* R4 - Audio Interface */
|
||||
[0x05] = { 0x0000, 0x003F }, /* R5 - Companding control */
|
||||
[0x06] = { 0x0000, 0x01FD }, /* R6 - Clock Gen control */
|
||||
[0x07] = { 0x0000, 0x000F }, /* R7 - Additional control */
|
||||
[0x08] = { 0x0000, 0x003F }, /* R8 - GPIO Control */
|
||||
[0x09] = { 0x0000, 0x0070 }, /* R9 - Jack Detect Control 1 */
|
||||
[0x0A] = { 0x0000, 0x004F }, /* R10 - DAC Control */
|
||||
[0x0B] = { 0x0000, 0x01FF }, /* R11 - Left DAC digital Vol */
|
||||
[0x0C] = { 0x0000, 0x01FF }, /* R12 - Right DAC digital vol */
|
||||
[0x0D] = { 0x0000, 0x00FF }, /* R13 - Jack Detect Control 2 */
|
||||
[0x0E] = { 0x0000, 0x01FB }, /* R14 - ADC Control */
|
||||
[0x0F] = { 0x0000, 0x01FF }, /* R15 - Left ADC Digital Vol */
|
||||
[0x10] = { 0x0000, 0x01FF }, /* R16 - Right ADC Digital Vol */
|
||||
[0x12] = { 0x0000, 0x017F }, /* R18 - EQ1 - low shelf */
|
||||
[0x13] = { 0x0000, 0x017F }, /* R19 - EQ2 - peak 1 */
|
||||
[0x14] = { 0x0000, 0x017F }, /* R20 - EQ3 - peak 2 */
|
||||
[0x15] = { 0x0000, 0x017F }, /* R21 - EQ4 - peak 3 */
|
||||
[0x16] = { 0x0000, 0x007F }, /* R22 - EQ5 - high shelf */
|
||||
[0x18] = { 0x0000, 0x01FF }, /* R24 - DAC Limiter 1 */
|
||||
[0x19] = { 0x0000, 0x007F }, /* R25 - DAC Limiter 2 */
|
||||
[0x1B] = { 0x0000, 0x01FF }, /* R27 - Notch Filter 1 */
|
||||
[0x1C] = { 0x0000, 0x017F }, /* R28 - Notch Filter 2 */
|
||||
[0x1D] = { 0x0000, 0x017F }, /* R29 - Notch Filter 3 */
|
||||
[0x1E] = { 0x0000, 0x017F }, /* R30 - Notch Filter 4 */
|
||||
[0x20] = { 0x0000, 0x01BF }, /* R32 - ALC control 1 */
|
||||
[0x21] = { 0x0000, 0x00FF }, /* R33 - ALC control 2 */
|
||||
[0x22] = { 0x0000, 0x01FF }, /* R34 - ALC control 3 */
|
||||
[0x23] = { 0x0000, 0x000F }, /* R35 - Noise Gate */
|
||||
[0x24] = { 0x0000, 0x001F }, /* R36 - PLL N */
|
||||
[0x25] = { 0x0000, 0x003F }, /* R37 - PLL K 1 */
|
||||
[0x26] = { 0x0000, 0x01FF }, /* R38 - PLL K 2 */
|
||||
[0x27] = { 0x0000, 0x01FF }, /* R39 - PLL K 3 */
|
||||
[0x29] = { 0x0000, 0x000F }, /* R41 - 3D control */
|
||||
[0x2A] = { 0x0000, 0x01E7 }, /* R42 - OUT4 to ADC */
|
||||
[0x2B] = { 0x0000, 0x01BF }, /* R43 - Beep control */
|
||||
[0x2C] = { 0x0000, 0x0177 }, /* R44 - Input ctrl */
|
||||
[0x2D] = { 0x0000, 0x01FF }, /* R45 - Left INP PGA gain ctrl */
|
||||
[0x2E] = { 0x0000, 0x01FF }, /* R46 - Right INP PGA gain ctrl */
|
||||
[0x2F] = { 0x0000, 0x0177 }, /* R47 - Left ADC BOOST ctrl */
|
||||
[0x30] = { 0x0000, 0x0177 }, /* R48 - Right ADC BOOST ctrl */
|
||||
[0x31] = { 0x0000, 0x007F }, /* R49 - Output ctrl */
|
||||
[0x32] = { 0x0000, 0x01FF }, /* R50 - Left mixer ctrl */
|
||||
[0x33] = { 0x0000, 0x01FF }, /* R51 - Right mixer ctrl */
|
||||
[0x34] = { 0x0000, 0x01FF }, /* R52 - LOUT1 (HP) volume ctrl */
|
||||
[0x35] = { 0x0000, 0x01FF }, /* R53 - ROUT1 (HP) volume ctrl */
|
||||
[0x36] = { 0x0000, 0x01FF }, /* R54 - LOUT2 (SPK) volume ctrl */
|
||||
[0x37] = { 0x0000, 0x01FF }, /* R55 - ROUT2 (SPK) volume ctrl */
|
||||
[0x38] = { 0x0000, 0x004F }, /* R56 - OUT3 mixer ctrl */
|
||||
[0x39] = { 0x0000, 0x00FF }, /* R57 - OUT4 (MONO) mix ctrl */
|
||||
[0x3D] = { 0x0000, 0x0100 } /* R61 - BIAS CTRL */
|
||||
};
|
||||
|
||||
/* vol/gain update regs */
|
||||
static const int vol_update_regs[] = {
|
||||
WM8983_LEFT_DAC_DIGITAL_VOL,
|
||||
@ -605,12 +545,19 @@ static int eqmode_put(struct snd_kcontrol *kcontrol,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static bool wm8983_readable(struct device *dev, unsigned int reg)
|
||||
static bool wm8983_writeable(struct device *dev, unsigned int reg)
|
||||
{
|
||||
if (reg > WM8983_MAX_REGISTER)
|
||||
return 0;
|
||||
|
||||
return wm8983_access_masks[reg].read != 0;
|
||||
switch (reg) {
|
||||
case WM8983_SOFTWARE_RESET ... WM8983_RIGHT_ADC_DIGITAL_VOL:
|
||||
case WM8983_EQ1_LOW_SHELF ... WM8983_DAC_LIMITER_2:
|
||||
case WM8983_NOTCH_FILTER_1 ... WM8983_NOTCH_FILTER_4:
|
||||
case WM8983_ALC_CONTROL_1 ... WM8983_PLL_K_3:
|
||||
case WM8983_3D_CONTROL ... WM8983_OUT4_MONO_MIX_CTRL:
|
||||
case WM8983_BIAS_CTRL:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
static int wm8983_dac_mute(struct snd_soc_dai *dai, int mute)
|
||||
@ -1048,8 +995,9 @@ static const struct regmap_config wm8983_regmap = {
|
||||
.reg_defaults = wm8983_defaults,
|
||||
.num_reg_defaults = ARRAY_SIZE(wm8983_defaults),
|
||||
.cache_type = REGCACHE_RBTREE,
|
||||
.max_register = WM8983_MAX_REGISTER,
|
||||
|
||||
.readable_reg = wm8983_readable,
|
||||
.writeable_reg = wm8983_writeable,
|
||||
};
|
||||
|
||||
#if defined(CONFIG_SPI_MASTER)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user