2013-07-19 16:59:32 +00:00
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/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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2014-09-08 16:57:28 +00:00
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* Copyright (c) 2014 The Linux Foundation. All rights reserved.
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*
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2013-07-19 16:59:32 +00:00
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "adreno_gpu.h"
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#include "msm_gem.h"
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2013-11-16 17:56:06 +00:00
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#include "msm_mmu.h"
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2013-07-19 16:59:32 +00:00
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#define RB_SIZE SZ_32K
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2016-11-28 19:28:33 +00:00
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#define RB_BLKSIZE 32
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2013-07-19 16:59:32 +00:00
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int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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switch (param) {
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case MSM_PARAM_GPU_ID:
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*value = adreno_gpu->info->revn;
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return 0;
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case MSM_PARAM_GMEM_SIZE:
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2013-12-05 22:39:53 +00:00
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*value = adreno_gpu->gmem;
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2013-07-19 16:59:32 +00:00
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return 0;
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2017-03-07 17:02:53 +00:00
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case MSM_PARAM_GMEM_BASE:
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*value = 0x100000;
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return 0;
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2014-02-04 19:16:04 +00:00
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case MSM_PARAM_CHIP_ID:
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*value = adreno_gpu->rev.patchid |
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(adreno_gpu->rev.minor << 8) |
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(adreno_gpu->rev.major << 16) |
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(adreno_gpu->rev.core << 24);
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return 0;
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2016-02-09 17:05:30 +00:00
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case MSM_PARAM_MAX_FREQ:
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*value = adreno_gpu->base.fast_rate;
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return 0;
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2016-02-22 11:26:21 +00:00
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case MSM_PARAM_TIMESTAMP:
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2017-07-28 10:47:08 +00:00
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if (adreno_gpu->funcs->get_timestamp) {
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int ret;
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pm_runtime_get_sync(&gpu->pdev->dev);
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ret = adreno_gpu->funcs->get_timestamp(gpu, value);
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pm_runtime_put_autosuspend(&gpu->pdev->dev);
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return ret;
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}
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2016-02-22 11:26:21 +00:00
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return -EINVAL;
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2013-07-19 16:59:32 +00:00
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default:
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DBG("%s: invalid param: %u", gpu->name, param);
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return -EINVAL;
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}
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}
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2017-10-16 14:13:15 +00:00
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const struct firmware *
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adreno_request_fw(struct adreno_gpu *adreno_gpu, const char *fwname)
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2017-10-16 13:22:38 +00:00
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{
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struct drm_device *drm = adreno_gpu->base.dev;
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2017-10-16 14:13:15 +00:00
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const struct firmware *fw = NULL;
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2017-10-16 13:22:38 +00:00
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int ret;
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2017-10-16 14:13:15 +00:00
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ret = request_firmware(&fw, fwname, drm->dev);
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if (ret) {
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dev_err(drm->dev, "failed to load %s: %d\n", fwname, ret);
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return ERR_PTR(ret);
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}
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return fw;
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}
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static int adreno_load_fw(struct adreno_gpu *adreno_gpu)
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{
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const struct firmware *fw;
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2017-10-16 13:22:38 +00:00
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if (adreno_gpu->pm4)
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return 0;
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2017-10-16 14:13:15 +00:00
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fw = adreno_request_fw(adreno_gpu, adreno_gpu->info->pm4fw);
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if (IS_ERR(fw))
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return PTR_ERR(fw);
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adreno_gpu->pm4 = fw;
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2017-10-16 13:22:38 +00:00
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2017-10-16 14:13:15 +00:00
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fw = adreno_request_fw(adreno_gpu, adreno_gpu->info->pfpfw);
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if (IS_ERR(fw)) {
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2017-10-16 13:22:38 +00:00
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release_firmware(adreno_gpu->pm4);
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adreno_gpu->pm4 = NULL;
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2017-10-16 14:13:15 +00:00
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return PTR_ERR(fw);
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2017-10-16 13:22:38 +00:00
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}
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2017-10-16 14:13:15 +00:00
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adreno_gpu->pfp = fw;
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2017-10-16 13:22:38 +00:00
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return 0;
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}
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2013-07-19 16:59:32 +00:00
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int adreno_hw_init(struct msm_gpu *gpu)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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2014-07-10 02:08:15 +00:00
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int ret;
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2013-07-19 16:59:32 +00:00
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DBG("%s", gpu->name);
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2017-10-16 13:22:38 +00:00
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ret = adreno_load_fw(adreno_gpu);
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if (ret)
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return ret;
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2017-06-13 22:52:54 +00:00
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ret = msm_gem_get_iova(gpu->rb->bo, gpu->aspace, &gpu->rb_iova);
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2014-07-10 02:08:15 +00:00
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if (ret) {
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gpu->rb_iova = 0;
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dev_err(gpu->dev->dev, "could not map ringbuffer: %d\n", ret);
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return ret;
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}
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2017-02-12 16:42:14 +00:00
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/* reset ringbuffer: */
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gpu->rb->cur = gpu->rb->start;
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/* reset completed fence seqno: */
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adreno_gpu->memptrs->fence = gpu->fctx->completed_fence;
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adreno_gpu->memptrs->rptr = 0;
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2013-07-19 16:59:32 +00:00
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/* Setup REG_CP_RB_CNTL: */
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2014-09-08 16:57:28 +00:00
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adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_CNTL,
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2013-07-19 16:59:32 +00:00
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/* size is log2(quad-words): */
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AXXX_CP_RB_CNTL_BUFSZ(ilog2(gpu->rb->size / 8)) |
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2016-02-19 00:50:02 +00:00
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AXXX_CP_RB_CNTL_BLKSZ(ilog2(RB_BLKSIZE / 8)) |
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(adreno_is_a430(adreno_gpu) ? AXXX_CP_RB_CNTL_NO_UPDATE : 0));
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2013-07-19 16:59:32 +00:00
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/* Setup ringbuffer address: */
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2016-11-28 19:28:29 +00:00
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adreno_gpu_write64(adreno_gpu, REG_ADRENO_CP_RB_BASE,
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REG_ADRENO_CP_RB_BASE_HI, gpu->rb_iova);
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2013-07-19 16:59:32 +00:00
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2016-11-28 19:28:29 +00:00
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if (!adreno_is_a430(adreno_gpu)) {
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adreno_gpu_write64(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR,
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REG_ADRENO_CP_RB_RPTR_ADDR_HI,
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rbmemptr(adreno_gpu, rptr));
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}
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2013-07-19 16:59:32 +00:00
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return 0;
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}
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static uint32_t get_wptr(struct msm_ringbuffer *ring)
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{
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return ring->cur - ring->start;
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}
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2016-02-19 00:50:02 +00:00
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/* Use this helper to read rptr, since a430 doesn't update rptr in memory */
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static uint32_t get_rptr(struct adreno_gpu *adreno_gpu)
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{
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if (adreno_is_a430(adreno_gpu))
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return adreno_gpu->memptrs->rptr = adreno_gpu_read(
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adreno_gpu, REG_ADRENO_CP_RB_RPTR);
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else
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return adreno_gpu->memptrs->rptr;
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}
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2013-07-19 16:59:32 +00:00
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uint32_t adreno_last_fence(struct msm_gpu *gpu)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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return adreno_gpu->memptrs->fence;
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}
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2013-08-24 18:20:38 +00:00
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void adreno_recover(struct msm_gpu *gpu)
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{
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struct drm_device *dev = gpu->dev;
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int ret;
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2017-02-10 20:36:33 +00:00
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// XXX pm-runtime?? we *need* the device to be off after this
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// so maybe continuing to call ->pm_suspend/resume() is better?
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2013-08-24 18:20:38 +00:00
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gpu->funcs->pm_suspend(gpu);
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gpu->funcs->pm_resume(gpu);
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2016-11-28 19:28:32 +00:00
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2017-02-10 20:36:33 +00:00
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ret = msm_gpu_hw_init(gpu);
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2013-08-24 18:20:38 +00:00
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if (ret) {
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dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
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/* hmm, oh well? */
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}
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}
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2016-05-03 13:46:49 +00:00
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void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
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2013-07-19 16:59:32 +00:00
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struct msm_file_private *ctx)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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struct msm_drm_private *priv = gpu->dev->dev_private;
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struct msm_ringbuffer *ring = gpu->rb;
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2016-06-01 18:17:40 +00:00
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unsigned i;
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2013-07-19 16:59:32 +00:00
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for (i = 0; i < submit->nr_cmds; i++) {
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switch (submit->cmd[i].type) {
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case MSM_SUBMIT_CMD_IB_TARGET_BUF:
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/* ignore IB-targets */
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break;
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case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
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/* ignore if there has not been a ctx switch: */
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if (priv->lastctx == ctx)
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break;
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case MSM_SUBMIT_CMD_BUF:
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2016-02-19 00:50:00 +00:00
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OUT_PKT3(ring, adreno_is_a430(adreno_gpu) ?
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CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2);
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2013-07-19 16:59:32 +00:00
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OUT_RING(ring, submit->cmd[i].iova);
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OUT_RING(ring, submit->cmd[i].size);
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2016-06-01 18:17:40 +00:00
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OUT_PKT2(ring);
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2013-07-19 16:59:32 +00:00
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break;
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}
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}
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OUT_PKT0(ring, REG_AXXX_CP_SCRATCH_REG2, 1);
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2016-03-15 22:26:28 +00:00
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OUT_RING(ring, submit->fence->seqno);
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2013-07-19 16:59:32 +00:00
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2014-09-08 19:40:16 +00:00
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if (adreno_is_a3xx(adreno_gpu) || adreno_is_a4xx(adreno_gpu)) {
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2013-07-19 16:59:32 +00:00
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/* Flush HLSQ lazy updates to make sure there is nothing
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* pending for indirect loads after the timestamp has
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* passed:
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*/
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OUT_PKT3(ring, CP_EVENT_WRITE, 1);
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OUT_RING(ring, HLSQ_FLUSH);
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OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
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OUT_RING(ring, 0x00000000);
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}
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OUT_PKT3(ring, CP_EVENT_WRITE, 3);
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OUT_RING(ring, CACHE_FLUSH_TS);
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OUT_RING(ring, rbmemptr(adreno_gpu, fence));
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2016-03-15 22:26:28 +00:00
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OUT_RING(ring, submit->fence->seqno);
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2013-07-19 16:59:32 +00:00
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/* we could maybe be clever and only CP_COND_EXEC the interrupt: */
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OUT_PKT3(ring, CP_INTERRUPT, 1);
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OUT_RING(ring, 0x80000000);
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2015-05-12 15:29:40 +00:00
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/* Workaround for missing irq issue on 8x16/a306. Unsure if the
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* root cause is a platform issue or some a306 quirk, but this
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* keeps things humming along:
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*/
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if (adreno_is_a306(adreno_gpu)) {
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OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
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OUT_RING(ring, 0x00000000);
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OUT_PKT3(ring, CP_INTERRUPT, 1);
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OUT_RING(ring, 0x80000000);
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}
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2013-07-19 16:59:32 +00:00
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#if 0
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if (adreno_is_a3xx(adreno_gpu)) {
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/* Dummy set-constant to trigger context rollover */
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OUT_PKT3(ring, CP_SET_CONSTANT, 2);
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OUT_RING(ring, CP_REG(REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG));
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OUT_RING(ring, 0x00000000);
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}
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#endif
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gpu->funcs->flush(gpu);
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}
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void adreno_flush(struct msm_gpu *gpu)
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{
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2014-09-08 16:57:28 +00:00
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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2016-12-20 15:54:29 +00:00
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uint32_t wptr;
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/*
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* Mask wptr value that we calculate to fit in the HW range. This is
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* to account for the possibility that the last command fit exactly into
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* the ringbuffer and rb->next hasn't wrapped to zero yet
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*/
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wptr = get_wptr(gpu->rb) & ((gpu->rb->size / 4) - 1);
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2013-07-19 16:59:32 +00:00
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/* ensure writes to ringbuffer have hit system memory: */
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mb();
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2014-09-08 16:57:28 +00:00
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adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_WPTR, wptr);
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2013-07-19 16:59:32 +00:00
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}
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2016-11-28 19:28:27 +00:00
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bool adreno_idle(struct msm_gpu *gpu)
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2013-07-19 16:59:32 +00:00
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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2014-01-11 21:11:59 +00:00
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uint32_t wptr = get_wptr(gpu->rb);
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2013-07-19 16:59:32 +00:00
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2014-01-11 21:11:59 +00:00
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/* wait for CP to drain ringbuffer: */
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2016-11-28 19:28:27 +00:00
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if (!spin_until(get_rptr(adreno_gpu) == wptr))
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return true;
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2013-07-19 16:59:32 +00:00
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/* TODO maybe we need to reset GPU here to recover from hang? */
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2016-11-28 19:28:27 +00:00
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DRM_ERROR("%s: timeout waiting to drain ringbuffer!\n", gpu->name);
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return false;
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2013-07-19 16:59:32 +00:00
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}
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#ifdef CONFIG_DEBUG_FS
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void adreno_show(struct msm_gpu *gpu, struct seq_file *m)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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2014-09-05 19:05:38 +00:00
|
|
|
int i;
|
2013-07-19 16:59:32 +00:00
|
|
|
|
|
|
|
seq_printf(m, "revision: %d (%d.%d.%d.%d)\n",
|
|
|
|
adreno_gpu->info->revn, adreno_gpu->rev.core,
|
|
|
|
adreno_gpu->rev.major, adreno_gpu->rev.minor,
|
|
|
|
adreno_gpu->rev.patchid);
|
|
|
|
|
|
|
|
seq_printf(m, "fence: %d/%d\n", adreno_gpu->memptrs->fence,
|
2016-03-15 21:22:13 +00:00
|
|
|
gpu->fctx->last_fence);
|
2016-02-19 00:50:02 +00:00
|
|
|
seq_printf(m, "rptr: %d\n", get_rptr(adreno_gpu));
|
2013-07-19 16:59:32 +00:00
|
|
|
seq_printf(m, "rb wptr: %d\n", get_wptr(gpu->rb));
|
2014-09-05 19:05:38 +00:00
|
|
|
|
|
|
|
/* dump these out in a form that can be parsed by demsm: */
|
|
|
|
seq_printf(m, "IO:region %s 00000000 00020000\n", gpu->name);
|
|
|
|
for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
|
|
|
|
uint32_t start = adreno_gpu->registers[i];
|
|
|
|
uint32_t end = adreno_gpu->registers[i+1];
|
|
|
|
uint32_t addr;
|
|
|
|
|
|
|
|
for (addr = start; addr <= end; addr++) {
|
|
|
|
uint32_t val = gpu_read(gpu, addr);
|
|
|
|
seq_printf(m, "IO:R %08x %08x\n", addr<<2, val);
|
|
|
|
}
|
|
|
|
}
|
2013-07-19 16:59:32 +00:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2015-04-19 14:14:09 +00:00
|
|
|
/* Dump common gpu status and scratch registers on any hang, to make
|
|
|
|
* the hangcheck logs more useful. The scratch registers seem always
|
|
|
|
* safe to read when GPU has hung (unlike some other regs, depending
|
|
|
|
* on how the GPU hung), and they are useful to match up to cmdstream
|
|
|
|
* dumps when debugging hangs:
|
|
|
|
*/
|
|
|
|
void adreno_dump_info(struct msm_gpu *gpu)
|
2013-12-22 15:29:43 +00:00
|
|
|
{
|
|
|
|
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
|
|
|
|
|
|
|
|
printk("revision: %d (%d.%d.%d.%d)\n",
|
|
|
|
adreno_gpu->info->revn, adreno_gpu->rev.core,
|
|
|
|
adreno_gpu->rev.major, adreno_gpu->rev.minor,
|
|
|
|
adreno_gpu->rev.patchid);
|
|
|
|
|
|
|
|
printk("fence: %d/%d\n", adreno_gpu->memptrs->fence,
|
2016-03-15 21:22:13 +00:00
|
|
|
gpu->fctx->last_fence);
|
2016-02-19 00:50:02 +00:00
|
|
|
printk("rptr: %d\n", get_rptr(adreno_gpu));
|
2013-12-22 15:29:43 +00:00
|
|
|
printk("rb wptr: %d\n", get_wptr(gpu->rb));
|
2015-04-19 14:14:09 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* would be nice to not have to duplicate the _show() stuff with printk(): */
|
|
|
|
void adreno_dump(struct msm_gpu *gpu)
|
|
|
|
{
|
|
|
|
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
|
|
|
|
int i;
|
|
|
|
|
2014-09-05 19:05:38 +00:00
|
|
|
/* dump these out in a form that can be parsed by demsm: */
|
|
|
|
printk("IO:region %s 00000000 00020000\n", gpu->name);
|
|
|
|
for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
|
|
|
|
uint32_t start = adreno_gpu->registers[i];
|
|
|
|
uint32_t end = adreno_gpu->registers[i+1];
|
|
|
|
uint32_t addr;
|
|
|
|
|
|
|
|
for (addr = start; addr <= end; addr++) {
|
|
|
|
uint32_t val = gpu_read(gpu, addr);
|
|
|
|
printk("IO:R %08x %08x\n", addr<<2, val);
|
|
|
|
}
|
|
|
|
}
|
2013-12-22 15:29:43 +00:00
|
|
|
}
|
|
|
|
|
2014-01-11 21:11:59 +00:00
|
|
|
static uint32_t ring_freewords(struct msm_gpu *gpu)
|
2013-07-19 16:59:32 +00:00
|
|
|
{
|
|
|
|
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
|
2014-01-11 21:11:59 +00:00
|
|
|
uint32_t size = gpu->rb->size / 4;
|
|
|
|
uint32_t wptr = get_wptr(gpu->rb);
|
2016-02-19 00:50:02 +00:00
|
|
|
uint32_t rptr = get_rptr(adreno_gpu);
|
2014-01-11 21:11:59 +00:00
|
|
|
return (rptr + (size - 1) - wptr) % size;
|
|
|
|
}
|
|
|
|
|
|
|
|
void adreno_wait_ring(struct msm_gpu *gpu, uint32_t ndwords)
|
|
|
|
{
|
|
|
|
if (spin_until(ring_freewords(gpu) >= ndwords))
|
|
|
|
DRM_ERROR("%s: timeout waiting for ringbuffer space\n", gpu->name);
|
2013-07-19 16:59:32 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
|
2014-09-05 19:03:40 +00:00
|
|
|
struct adreno_gpu *adreno_gpu, const struct adreno_gpu_funcs *funcs)
|
2013-07-19 16:59:32 +00:00
|
|
|
{
|
2014-09-05 19:03:40 +00:00
|
|
|
struct adreno_platform_config *config = pdev->dev.platform_data;
|
2017-05-08 20:35:03 +00:00
|
|
|
struct msm_gpu_config adreno_gpu_config = { 0 };
|
2014-09-05 19:03:40 +00:00
|
|
|
struct msm_gpu *gpu = &adreno_gpu->base;
|
2014-09-05 17:30:27 +00:00
|
|
|
int ret;
|
2013-07-19 16:59:32 +00:00
|
|
|
|
2014-09-05 19:03:40 +00:00
|
|
|
adreno_gpu->funcs = funcs;
|
|
|
|
adreno_gpu->info = adreno_info(config->rev);
|
|
|
|
adreno_gpu->gmem = adreno_gpu->info->gmem;
|
|
|
|
adreno_gpu->revn = adreno_gpu->info->revn;
|
|
|
|
adreno_gpu->rev = config->rev;
|
|
|
|
|
|
|
|
gpu->fast_rate = config->fast_rate;
|
|
|
|
gpu->bus_freq = config->bus_freq;
|
2015-06-04 14:26:37 +00:00
|
|
|
#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
|
2014-09-05 19:03:40 +00:00
|
|
|
gpu->bus_scale_table = config->bus_scale_table;
|
|
|
|
#endif
|
|
|
|
|
2017-03-07 17:02:54 +00:00
|
|
|
DBG("fast_rate=%u, slow_rate=27000000, bus_freq=%u",
|
|
|
|
gpu->fast_rate, gpu->bus_freq);
|
2013-07-19 16:59:32 +00:00
|
|
|
|
2017-05-08 20:35:03 +00:00
|
|
|
adreno_gpu_config.ioname = "kgsl_3d0_reg_memory";
|
|
|
|
adreno_gpu_config.irqname = "kgsl_3d0_irq";
|
|
|
|
|
|
|
|
adreno_gpu_config.va_start = SZ_16M;
|
|
|
|
adreno_gpu_config.va_end = 0xffffffff;
|
|
|
|
|
|
|
|
adreno_gpu_config.ringsz = RB_SIZE;
|
|
|
|
|
2017-07-27 16:42:39 +00:00
|
|
|
pm_runtime_set_autosuspend_delay(&pdev->dev, DRM_MSM_INACTIVE_PERIOD);
|
|
|
|
pm_runtime_use_autosuspend(&pdev->dev);
|
|
|
|
pm_runtime_enable(&pdev->dev);
|
|
|
|
|
2014-10-31 15:50:55 +00:00
|
|
|
ret = msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base,
|
2017-05-08 20:35:03 +00:00
|
|
|
adreno_gpu->info->name, &adreno_gpu_config);
|
2014-10-31 15:50:55 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2017-07-27 16:42:40 +00:00
|
|
|
adreno_gpu->memptrs = msm_gem_kernel_new(drm,
|
|
|
|
sizeof(*adreno_gpu->memptrs), MSM_BO_UNCACHED, gpu->aspace,
|
|
|
|
&adreno_gpu->memptrs_bo, &adreno_gpu->memptrs_iova);
|
2013-07-19 16:59:32 +00:00
|
|
|
|
2016-05-24 22:29:38 +00:00
|
|
|
if (IS_ERR(adreno_gpu->memptrs)) {
|
2017-07-27 16:42:40 +00:00
|
|
|
ret = PTR_ERR(adreno_gpu->memptrs);
|
|
|
|
adreno_gpu->memptrs = NULL;
|
|
|
|
dev_err(drm->dev, "could not allocate memptrs: %d\n", ret);
|
2013-07-19 16:59:32 +00:00
|
|
|
}
|
|
|
|
|
2017-07-27 16:42:40 +00:00
|
|
|
return ret;
|
2013-07-19 16:59:32 +00:00
|
|
|
}
|
|
|
|
|
2017-02-06 17:39:29 +00:00
|
|
|
void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu)
|
2013-07-19 16:59:32 +00:00
|
|
|
{
|
2017-02-06 17:39:29 +00:00
|
|
|
struct msm_gpu *gpu = &adreno_gpu->base;
|
|
|
|
|
|
|
|
if (adreno_gpu->memptrs_bo) {
|
|
|
|
if (adreno_gpu->memptrs)
|
|
|
|
msm_gem_put_vaddr(adreno_gpu->memptrs_bo);
|
|
|
|
|
|
|
|
if (adreno_gpu->memptrs_iova)
|
2017-06-13 15:07:08 +00:00
|
|
|
msm_gem_put_iova(adreno_gpu->memptrs_bo, gpu->aspace);
|
2017-02-06 17:39:29 +00:00
|
|
|
|
|
|
|
drm_gem_object_unreference_unlocked(adreno_gpu->memptrs_bo);
|
|
|
|
}
|
|
|
|
release_firmware(adreno_gpu->pm4);
|
|
|
|
release_firmware(adreno_gpu->pfp);
|
2016-05-26 20:24:35 +00:00
|
|
|
|
2017-02-06 17:39:29 +00:00
|
|
|
msm_gpu_cleanup(gpu);
|
2013-07-19 16:59:32 +00:00
|
|
|
}
|